內容目錄
今天
您說
Keypad SafeLocker Keypad SafeLocker has 2 main module Keypad(frontEnd) and Combo(backend), communicated with {valid,keycode} transfer bus io[12:8].
1. Keypad module:
4×4 鍵盤 DE10-Lite
- io[7:4]: row scan with OC,
- io[3:0] col read scan value weak pull high.
- output key_valid and 4 bit keycode: {valid,keycode} on io[12:8]. key code (in 4bit hex)
- scan: R3C3: is 4’h1 R3C2: is 4’h2 R3C1: is 4’h3 R3C0: is 4’hA R2C3: is 4’h4 R2C2: is 4’h5 R2C1: is 4’h6 R2C0: is 4’hB R1C3: is 4’h7 R1C2: is 4’h8 R1C1: is 4’h9 R1C0: is 4’hC R0C3: is 4’hE R0C2: is 4’h0 R0C1: is 4’hF R0C0: is 4’hD
- module do rowscan, debouncing, xfer, waitrelease, debouncing with FSM, thus waiting counter can be only 1set with different value.
- Each rowscan should wait 1ms for stable, then get key value.
- If had key pressed, get it then debouncing for 10ms.
- If success get, do xfer for 0.5ms, otherwise scan next.
- after xfer, wait key release. need release for 20ms debouncing.
- then back to scan next line. debug the {valid,keycode} on LEDR[9:5]
2. Combo module:
- receive {valid,keycode} from keypad for password/attempt entering.
- FSM: open – getPSW – locked – getATT, then open if PSW/ATT match, locked if unmatch.
- keycode 4’hE means clear, 4’hF means enter.
- 6 digits length for PSW and ATT.
- HEX5~HEX0 display shows
_OPEn_on open state, showsLOCHEOon locked state. - on getPSW and getATT state, wait 6 digit number enter.
- the getCodeFSM shows current digits have on HEX5~HEX0.
- if <6 digit, show _ at next enter HEX, follows empty. if >6 digits, keep the last 6 digits on screen.
- if 4’hE pressed, delete 1 digit.
- if no digits, go back to the open or locked state and show message defined there.
- if 4’hF pressed, check entered PSW or ATT length. only 6 digits accept. otherwise show _Err for 1 second, then back to the open or locked state.
- debug the current Combo state on LEDR[1:0]
Copilot 說
Thanks for sharing the detailed design of your Keypad SafeLocker system! Here’s a breakdown and interpretation of the architecture and behavior, along with some implementation insights to help you debug or refine it:
🔐 System Overview
The SafeLocker consists of two main modules:
1. Keypad Module (FrontEnd)
Handles physical key scanning and debouncing.
🔧 Hardware Interface
- DE10-Lite FPGA Pins:
io[7:4]: Row scan outputs (Open Collector)io[3:0]: Column inputs (weak pull-up)io[12:8]: Output busvalid, keycode
🔢 Key Mapping (Hex Codes)
| Row | C3 | C2 | C1 | C0 |
|---|---|---|---|---|
| R3 | 1 | 2 | 3 | A |
| R2 | 4 | 5 | 6 | B |
| R1 | 7 | 8 | 9 | C |
| R0 | E | 0 | F | D |
⏱ FSM Timing Behavior
- Row Scan: Wait 1ms for stable signal.
- Key Press Detected:
- Debounce for 10ms.
- If valid, transfer
valid, keycodefor 0.5ms. - If not valid, scan next row.
- Post Transfer:
- Wait for key release (20ms debounce).
- Resume scanning.
🧪 Debug Output
valid, keycodeshown onLEDR[9:5].
2. Combo Module (BackEnd)
Handles password entry and access control.
🔁 FSM States
open→getPSW→locked→getATT→open(if match) orlocked(if not)
🔐 Keycode Functions
4'hE: Clear (delete last digit)4'hF: Enter (submit input)
🔢 Password/Attempt Rules
- Must be 6 digits.
- Input shown on
HEX5~HEX0:<6 digits: Show_at next digit, rest blank.>6 digits: Keep last 6 digits.
4'hE: Delete one digit. If empty, return toopenorlocked.4'hF: Validate length:- If not 6 digits → show
_Errfor 1s, then return. - If 6 digits → compare with stored PSW/ATT.
- If not 6 digits → show
🧪 Debug Output
- Combo FSM state shown on
LEDR[1:0].
🧠 Implementation Tips
FSM Design
Use a single counter module with parameterized delay values for debounce and timing control. This keeps your design modular and avoids duplication.
Keypad Scan Logic
- Use a rotating row scan (e.g., one-hot encoding).
- For each row:
- Drive low, read columns.
- If column low → key press detected.
- Map row/col to keycode using lookup table.
Combo FSM
- Use a shift register or array to store entered digits.
- On
4'hE, pop last digit. - On
4'hF, check length and compare. - Use a timer FSM to show
_Errfor 1s.
Would you like help writing the Verilog code for either module? Or maybe simulate the FSM behavior to verify transitions?
在頁面中編輯
您說
creat sv for both block, simulate on same DE10-lite board.
Copilot 說
Great! Let’s build SystemVerilog modules for both the Keypad and Combo blocks, and simulate them together on the DE10-Lite FPGA. Here’s a complete setup:
🧩 1. Keypad Module (Keypad.sv)
This module scans a 4×4 keypad, debounces input, and outputs valid, keycode on io[12:8].
systemverilog
複製
module Keypad (
input logic clk, rst,
inout logic [7:4] row, // Open collector row scan
input logic [3:0] col, // Column input
output logic [12:8] io, // {valid, keycode}
output logic [9:5] LEDR // Debug output
);
typedef enum logic [2:0] {
SCAN, DEBOUNCE_PRESS, TRANSFER, WAIT_RELEASE, DEBOUNCE_RELEASE
} state_t;
state_t state;
logic [3:0] current_row;
logic [3:0] keycode;
logic valid;
logic [15:0] debounce_counter;
// Keycode lookup table
function logic [3:0] get_keycode(input logic [3:0] r, input logic [3:0] c);
case ({r, c})
8'h33: return 4'h1; 8'h32: return 4'h2; 8'h31: return 4'h3; 8'h30: return 4'hA;
8'h23: return 4'h4; 8'h22: return 4'h5; 8'h21: return 4'h6; 8'h20: return 4'hB;
8'h13: return 4'h7; 8'h12: return 4'h8; 8'h11: return 4'h9; 8'h10: return 4'hC;
8'h03: return 4'hE; 8'h02: return 4'h0; 8'h01: return 4'hF; 8'h00: return 4'hD;
default: return 4'hF;
endcase
endfunction
always_ff @(posedge clk or posedge rst) begin
if (rst) begin
state <= SCAN;
current_row <= 4'b1110;
debounce_counter <= 0;
valid <= 0;
end else begin
case (state)
SCAN: begin
debounce_counter <= debounce_counter + 1;
if (debounce_counter == 1000) begin // 1ms
if (col != 4'b1111) begin
keycode <= get_keycode(current_row, col);
state <= DEBOUNCE_PRESS;
debounce_counter <= 0;
end else begin
current_row <= {current_row[2:0], current_row[3]};
debounce_counter <= 0;
end
end
end
DEBOUNCE_PRESS: begin
debounce_counter <= debounce_counter + 1;
if (debounce_counter == 10000) begin // 10ms
valid <= 1;
state <= TRANSFER;
debounce_counter <= 0;
end
end
TRANSFER: begin
debounce_counter <= debounce_counter + 1;
if (debounce_counter == 500) begin // 0.5ms
valid <= 0;
state <= WAIT_RELEASE;
debounce_counter <= 0;
end
end
WAIT_RELEASE: begin
if (col == 4'b1111) begin
state <= DEBOUNCE_RELEASE;
debounce_counter <= 0;
end
end
DEBOUNCE_RELEASE: begin
debounce_counter <= debounce_counter + 1;
if (debounce_counter == 20000) begin // 20ms
state <= SCAN;
debounce_counter <= 0;
end
end
endcase
end
end
assign io = {valid, keycode};
assign LEDR[9:5] = io[12:8];
assign row = current_row;
endmodule🔐 2. Combo Module (Combo.sv)
This module receives valid, keycode and manages password entry and access control.
systemverilog
複製
module Combo (
input logic clk, rst,
input logic [4:0] keycode,
input logic valid,
output logic [6:0] HEX[5:0],
output logic [1:0] LEDR
);
typedef enum logic [1:0] {
OPEN, GET_PSW, LOCKED, GET_ATT
} state_t;
state_t state;
logic [3:0] psw[5:0], att[5:0], input_buf[5:0];
logic [2:0] input_count;
logic show_err;
logic [15:0] err_timer;
function logic match(input logic [3:0] a[5:0], input logic [3:0] b[5:0]);
for (int i = 0; i < 6; i++) if (a[i] != b[i]) return 0;
return 1;
endfunction
always_ff @(posedge clk or posedge rst) begin
if (rst) begin
state <= OPEN;
input_count <= 0;
show_err <= 0;
err_timer <= 0;
end else begin
if (valid) begin
case (keycode)
4'hE: begin
if (input_count > 0) input_count--;
else state <= (state == GET_PSW) ? OPEN : LOCKED;
end
4'hF: begin
if (input_count == 6) begin
if (state == GET_PSW) begin
for (int i = 0; i < 6; i++) psw[i] <= input_buf[i];
state <= LOCKED;
end else if (state == GET_ATT) begin
for (int i = 0; i < 6; i++) att[i] <= input_buf[i];
state <= match(psw, att) ? OPEN : LOCKED;
end
input_count <= 0;
end else begin
show_err <= 1;
err_timer <= 0;
end
end
default: begin
if (input_count < 6) begin
input_buf[input_count] <= keycode;
input_count++;
end
end
endcase
end
if (show_err) begin
err_timer <= err_timer + 1;
if (err_timer == 50000) begin // 1s
show_err <= 0;
state <= (state == GET_PSW) ? OPEN : LOCKED;
input_count <= 0;
end
end
end
end
assign LEDR = state;
// HEX display logic (simplified)
always_comb begin
for (int i = 0; i < 6; i++) begin
if (show_err) HEX[i] = 7'h79; // "_Err"
else if (state == OPEN) HEX[i] = 7'h3F; // "O"
else if (state == LOCKED) HEX[i] = 7'h38; // "L"
else HEX[i] = (i < input_count) ? input_buf[i] : 7'h00;
end
end
endmodule🧪 Integration & Simulation
To simulate both modules on the DE10-Lite board:
- Top Module (
SafeLockerTop.sv):- Instantiate both
KeypadandCombo. - Connect
io[12:8]from Keypad to Combo. - Map
LEDR,HEX, andioto board pins.
- Instantiate both
- Constraints File (
.qsf):- Assign
io[12:0],LEDR[9:0],HEX[5:0]to physical pins.
- Assign
- Simulation:
- Use ModelSim or Quartus simulation tools.
- Stimulate
colinputs to simulate key presses. - Observe
LEDRandHEXoutputs.
Would you like me to generate the top-level module and testbench next?
在頁面中編輯
您說
top-level module on Quartus
Copilot 說
Perfect! Here’s a top-level SystemVerilog module that integrates both the Keypad and Combo modules for your Keypad SafeLocker project on the DE10-Lite board. This module connects the physical I/O pins, wires up the internal buses, and prepares the design for synthesis in Quartus.
🧩 SafeLockerTop.sv
systemverilog
複製
module SafeLockerTop (
input logic CLOCK_50, // Main clock
input logic KEY0, // Reset button
inout logic [7:4] GPIO_ROW, // Keypad row scan (OC)
input logic [3:0] GPIO_COL, // Keypad column input
output logic [9:0] LEDR, // Debug LEDs
output logic [6:0] HEX0,
output logic [6:0] HEX1,
output logic [6:0] HEX2,
output logic [6:0] HEX3,
output logic [6:0] HEX4,
output logic [6:0] HEX5
);
// Internal signals
logic [12:8] io_bus; // {valid, keycode}
logic [4:0] keycode;
logic valid;
// Instantiate Keypad module
Keypad keypad_inst (
.clk(CLOCK_50),
.rst(~KEY0),
.row(GPIO_ROW),
.col(GPIO_COL),
.io(io_bus),
.LEDR(LEDR[9:5])
);
assign valid = io_bus[12];
assign keycode = io_bus[11:8];
// Instantiate Combo module
Combo combo_inst (
.clk(CLOCK_50),
.rst(~KEY0),
.keycode(keycode),
.valid(valid),
.HEX({HEX5, HEX4, HEX3, HEX2, HEX1, HEX0}),
.LEDR(LEDR[1:0])
);
endmodule🛠 Quartus Setup Tips
1. Project Creation
- Create a new Quartus project named
SafeLocker. - Add
SafeLockerTop.sv,Keypad.sv, andCombo.svto the project.
2. Pin Assignments
Use the Pin Planner or .qsf file to assign physical pins:
| Signal | DE10-Lite Pin Name | Notes |
|---|---|---|
CLOCK_50 |
PIN_A9 | 50 MHz clock |
KEY0 |
PIN_N2 | Push button (active low) |
GPIO_ROW[7:4] |
PINs (e.g., D13, E13, F13, G13) | Row scan pins |
GPIO_COL[3:0] |
PINs (e.g., H13, J13, K13, L13) | Column input pins |
LEDR[9:0] |
PINs (e.g., M1–M10) | Debug LEDs |
HEX[5:0] |
PINs for 7-seg displays | Assign accordingly |
3. Compilation
- Compile the project.
- Check for timing violations and resolve if needed.
- Use the TimeQuest Timing Analyzer to verify debounce delays.
4. Simulation (Optional)
- Use ModelSim to simulate
SafeLockerTop. - Stimulate
GPIO_COLto emulate key presses. - Observe
LEDRandHEXoutputs.
Would you like help writing the .qsf pin assignment file or a testbench for simulation?
在頁面中編輯
您說
50MHz clock
Copilot 說
The 50 MHz clock on the DE10-Lite board is your main timing source, and it’s perfect for driving FSMs and debounce counters in your SafeLocker design.
To use it effectively in your SystemVerilog modules:
🕒 Timing Reference
- Clock Frequency: 50 MHz
- Clock Period:
T=150×106=20 ns
So every tick of the clock is 20 nanoseconds.
⏱ Delay Calculations
To implement delays like 1ms, 10ms, etc., you’ll need counters:
| Delay | Clock Cycles Needed | Counter Width |
|---|---|---|
| 0.5 ms | 25,000 cycles | 15 bits |
| 1 ms | 50,000 cycles | 16 bits |
| 10 ms | 500,000 cycles | 19 bits |
| 20 ms | 1,000,000 cycles | 20 bits |
| 1 sec | 50,000,000 cycles | 26 bits |
Use these values to size your debounce and wait counters in the FSMs.
🧠 Example Counter Snippet
logic [19:0] counter;
always_ff @(posedge clk or posedge rst) begin
if (rst)
counter <= 0;
else if (counter < 500_000) // 10ms
counter <= counter + 1;
else
counter <= 0; // Done waiting
endIf you’d like, I can help you refactor your FSMs to use a shared timing module or generate a parameterized delay module for reuse. Want to go that route?
.
.
.
.
==> worked keypad.sv :
module Keypad (
input logic clk, rst,
inout logic [7:4] row, // Open collector row scan
input logic [3:0] col, // Column input
output logic [4:0] io, // {valid, keycode}
output logic [9:5] debugled // Debug led output
);
typedef enum logic [2:0] {
SCAN, DEBOUNCE_PRESS, TRANSFER, WAIT_RELEASE, RESTART
} state_t;
state_t state;
logic [3:0] current_row;
logic [3:0] keycode;
logic valid;
// large delay/debounce counter for all state. in 50MHz system, 1ms take 50,000 cycles
// since designed for 20ms max. => take 1,000,000 cycles, need 20 bits...
// just one counter be needed in this FSM sequence flow...
logic [19:0] debounce_counter;
// Keycode lookup function
function logic [3:0] get_keycode(input logic [3:0] r, input logic [3:0] c);
case ({r, c})
8'b0111_0111: return 4'h1; 8'b0111_1011: return 4'h2; 8'b0111_1101: return 4'h3; 8'b0111_1110: return 4'hA;
8'b1011_0111: return 4'h4; 8'b1011_1011: return 4'h5; 8'b1011_1101: return 4'h6; 8'b1011_1110: return 4'hB;
8'b1101_0111: return 4'h7; 8'b1101_1011: return 4'h8; 8'b1101_1101: return 4'h9; 8'b1101_1110: return 4'hC;
8'b1110_0111: return 4'hE; 8'b1110_1011: return 4'h0; 8'b1110_1101: return 4'hF; 8'b1110_1110: return 4'hD;
default: return 4'hA; // err? give a non-noise signal for test...
endcase
endfunction
// FSM to get and transfer key value
always_ff @(posedge clk or posedge rst) begin
if (rst) begin
state <= RESTART; // do samething as restart FSM...
end else begin
case (state)
SCAN: begin // add 1ms row signal wait, 4 rows need 4ms in one scan loop...
debounce_counter <= debounce_counter + 1;
// wait 1ms for scan signal stable (L/R/C issue for long wire)
if (debounce_counter == 1*50000) begin // 1ms
if (col != 4'b1111) begin // key be scaned?
keycode <= get_keycode(current_row, col);
state <= DEBOUNCE_PRESS; // not valid before measure...
debounce_counter <= 0;
end else begin // change to next scan pin (through current_row bit rotate)
current_row <= {current_row[2:0], current_row[3]};
debounce_counter <= 0;
end
end
end
DEBOUNCE_PRESS: begin // mechanically bouncing issue, might longer if meet bad keypad...
debounce_counter <= debounce_counter + 1;
if (debounce_counter == 10*50000) begin // 10ms
// 10ms debounce check. if fail, do next scan, else do keycode xfer.
state <= (keycode==get_keycode(current_row, col))? TRANSFER:WAIT_RELEASE;
debounce_counter <= 0;
end
end
TRANSFER: begin // doing > > 3 cycle data transfer.
debounce_counter <= debounce_counter + 1;
valid <= 1; // xfer keycode, keep signal during transfer cycles.
if (debounce_counter == 50000/2) begin // 0.5ms > > 3 cycle in spec., but longer is better for slow receiver
state <= WAIT_RELEASE;
debounce_counter <= 0;
end
end
WAIT_RELEASE: begin // after transfer or error key signal, wait the key up
debounce_counter <= debounce_counter + 1;
if (col == 4'b1111) valid <= 0; // had released? invalid transfer signal
else debounce_counter <= 0; // any noise in debouncing? keep waitting...
if (debounce_counter == 20*50000) begin // 20ms no key ==> done, no next scan...
state <= SCAN;
debounce_counter <= 0;
end
end
RESTART: begin // initialize and start scan
state <= SCAN;
current_row <= 4'b1110; // scan row initialize
debounce_counter <= 0; // delay/debug counter reset
valid <= 0;
keycode <=0;
end
default: state <= RESTART; // take care all of the illeagle states in FSM!!
endcase
end
end
assign io = {valid, keycode}; // signal to other module/boards...
assign debugled = io;
assign row = current_row;
endmodule==> worked Combo.sv :
module Combo (
input logic clk, rst,
input logic [3:0] keycode,
input logic valid,
output logic [7:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5,
output logic [1:0] debugled
);
typedef enum logic [1:0] {
OPEN, GET_PSW, LOCKED, GET_ATT
} state_t;
state_t state;
logic [3:0] psw[5:0], att[5:0], input_buf[5:0];
logic [2:0] input_count;
logic show_err;
logic [25:0] err_timer;
logic wait_release;
function logic match(input logic [3:0] a[5:0], input logic [3:0] b[5:0]);
for (int i = 0; i < 6; i++) if (a[i] != b[i]) return 0;
return 1;
endfunction
function logic [7:0] seg_decode(input logic [3:0] val);
case (val)
4'h0: seg_decode = 8'b11000000;
4'h1: seg_decode = 8'b11111001;
4'h2: seg_decode = 8'b10100100;
4'h3: seg_decode = 8'b10110000;
4'h4: seg_decode = 8'b10011001;
4'h5: seg_decode = 8'b10010010;
4'h6: seg_decode = 8'b10000010;
4'h7: seg_decode = 8'b11111000;
4'h8: seg_decode = 8'b10000000;
4'h9: seg_decode = 8'b10010000;
4'hA: seg_decode = 8'b10001000;
4'hB: seg_decode = 8'b10000011;
4'hC: seg_decode = 8'b11000110;
4'hD: seg_decode = 8'b10100001;
4'hE: seg_decode = 8'b10000110;
4'hF: seg_decode = 8'b10001110;
default: seg_decode = 8'b11111111;
endcase
endfunction
function logic [7:0] char_decode(input byte ch);
case (ch)
"_": char_decode = 8'b11110111;
"O": char_decode = 8'b11000000;
"P": char_decode = 8'b10001100;
"E": char_decode = 8'b10000110;
"N": char_decode = 8'b10101011;
"L": char_decode = 8'b11000111;
"C": char_decode = 8'b11000110;
"H": char_decode = 8'b10001001;
"r": char_decode = 8'b10101111;
"D": char_decode = 8'b10100001;
default: char_decode = 8'b11111111;
endcase
endfunction
always_ff @(posedge clk or posedge rst) begin
if (rst) begin
state <= OPEN;
input_count <= 0;
show_err <= 0;
err_timer <= 0;
wait_release <= 0;
end else begin
case (state)
OPEN: begin
if (valid && !wait_release) begin
state <= GET_PSW;
wait_release <= 1;
end else if (!valid) begin
wait_release <= 0;
end
end
LOCKED: begin
if (valid && !wait_release) begin
state <= GET_ATT;
wait_release <= 1;
end else if (!valid) begin
wait_release <= 0;
end
end
GET_PSW, GET_ATT: begin
if (show_err) begin
err_timer <= err_timer + 1;
if (err_timer == 50_000_000) begin
show_err <= 0;
input_count <= 0;
state <= (state == GET_PSW) ? OPEN : LOCKED;
end
end else if (valid && !wait_release) begin
wait_release <= 1;
if (keycode == 4'hE) begin
if (input_count > 0) begin
input_count <= input_count - 1;
input_buf[input_count - 1] <= 4'hF;
end else begin
state <= (state == GET_PSW) ? OPEN : LOCKED;
end
end else if (keycode == 4'hF) begin
if (input_count == 6) begin
if (state == GET_PSW) begin
for (int i = 0; i < 6; i++) psw[i] <= input_buf[i];
state <= LOCKED;
end else begin
for (int i = 0; i < 6; i++) att[i] <= input_buf[i];
state <= match(psw, att) ? OPEN : LOCKED;
end
input_count <= 0;
end else begin
show_err <= 1;
err_timer <= 0;
end
end else begin
if (input_count < 6) begin
input_buf[input_count] <= keycode;
input_count <= input_count + 1;
end else begin
for (int i = 0; i < 5; i++) input_buf[i] <= input_buf[i+1];
input_buf[5] <= keycode;
end
end
end else if (!valid) begin
wait_release <= 0;
end
end
endcase
end
end
assign LEDR = state;
always_comb begin
if (show_err) begin
HEX5 = char_decode("_");
HEX4 = char_decode("E");
HEX3 = char_decode("r");
HEX2 = char_decode("r");
HEX1 = char_decode("_");
HEX0 = char_decode(" ");
end else case (state)
OPEN: begin
HEX5 = char_decode("_");
HEX4 = char_decode("O");
HEX3 = char_decode("P");
HEX2 = char_decode("E");
HEX1 = char_decode("N");
HEX0 = char_decode("_");
end
LOCKED: begin
HEX5 = char_decode("L");
HEX4 = char_decode("O");
HEX3 = char_decode("C");
HEX2 = char_decode("H");
HEX1 = char_decode("E");
HEX0 = char_decode("D");
end
GET_PSW, GET_ATT: begin
HEX5 = (input_count > 0) ? seg_decode(input_buf[0]) : (input_count == 0) ? char_decode("_") : 8'hFF;
HEX4 = (input_count > 1) ? seg_decode(input_buf[1]) : (input_count == 1) ? char_decode("_") : 8'hFF;
HEX3 = (input_count > 2) ? seg_decode(input_buf[2]) : (input_count == 2) ? char_decode("_") : 8'hFF;
HEX2 = (input_count > 3) ? seg_decode(input_buf[3]) : (input_count == 3) ? char_decode("_") : 8'hFF;
HEX1 = (input_count > 4) ? seg_decode(input_buf[4]) : (input_count == 4) ? char_decode("_") : 8'hFF;
HEX0 = (input_count > 5) ? seg_decode(input_buf[5]) : (input_count == 5) ? char_decode("_") : 8'hFF;
end
endcase
end
endmodule
Top: DE10_LITE_Golden_Top.v
// ============================================================================
// Ver :| Author :| Mod. Date :| Changes Made:
// V1.1 :| Alexandra Du :| 06/01/2016:| Added Verilog file
// ============================================================================
//=======================================================
// This code is generated by Terasic System Builder
//=======================================================
`define ENABLE_ADC_CLOCK
`define ENABLE_CLOCK1
`define ENABLE_CLOCK2
`define ENABLE_SDRAM
`define ENABLE_HEX0
`define ENABLE_HEX1
`define ENABLE_HEX2
`define ENABLE_HEX3
`define ENABLE_HEX4
`define ENABLE_HEX5
`define ENABLE_KEY
`define ENABLE_LED
`define ENABLE_SW
`define ENABLE_VGA
`define ENABLE_ACCELEROMETER
`define ENABLE_ARDUINO
`define ENABLE_GPIO
module DE10_LITE_Golden_Top(
//////////// ADC CLOCK: 3.3-V LVTTL //////////
`ifdef ENABLE_ADC_CLOCK
input ADC_CLK_10,
`endif
//////////// CLOCK 1: 3.3-V LVTTL //////////
`ifdef ENABLE_CLOCK1
input MAX10_CLK1_50,
`endif
//////////// CLOCK 2: 3.3-V LVTTL //////////
`ifdef ENABLE_CLOCK2
input MAX10_CLK2_50,
`endif
//////////// SDRAM: 3.3-V LVTTL //////////
`ifdef ENABLE_SDRAM
output [12:0] DRAM_ADDR,
output [1:0] DRAM_BA,
output DRAM_CAS_N,
output DRAM_CKE,
output DRAM_CLK,
output DRAM_CS_N,
inout [15:0] DRAM_DQ,
output DRAM_LDQM,
output DRAM_RAS_N,
output DRAM_UDQM,
output DRAM_WE_N,
`endif
//////////// SEG7: 3.3-V LVTTL //////////
`ifdef ENABLE_HEX0
output [7:0] HEX0,
`endif
`ifdef ENABLE_HEX1
output [7:0] HEX1,
`endif
`ifdef ENABLE_HEX2
output [7:0] HEX2,
`endif
`ifdef ENABLE_HEX3
output [7:0] HEX3,
`endif
`ifdef ENABLE_HEX4
output [7:0] HEX4,
`endif
`ifdef ENABLE_HEX5
output [7:0] HEX5,
`endif
//////////// KEY: 3.3 V SCHMITT TRIGGER //////////
`ifdef ENABLE_KEY
input [1:0] KEY,
`endif
//////////// LED: 3.3-V LVTTL //////////
`ifdef ENABLE_LED
output [9:0] LEDR,
`endif
//////////// SW: 3.3-V LVTTL //////////
`ifdef ENABLE_SW
input [9:0] SW,
`endif
//////////// VGA: 3.3-V LVTTL //////////
`ifdef ENABLE_VGA
output [3:0] VGA_B,
output [3:0] VGA_G,
output VGA_HS,
output [3:0] VGA_R,
output VGA_VS,
`endif
//////////// Accelerometer: 3.3-V LVTTL //////////
`ifdef ENABLE_ACCELEROMETER
output GSENSOR_CS_N,
input [2:1] GSENSOR_INT,
output GSENSOR_SCLK,
inout GSENSOR_SDI,
inout GSENSOR_SDO,
`endif
//////////// Arduino: 3.3-V LVTTL //////////
`ifdef ENABLE_ARDUINO
inout [15:0] ARDUINO_IO,
inout ARDUINO_RESET_N,
`endif
//////////// GPIO, GPIO connect to GPIO Default: 3.3-V LVTTL //////////
`ifdef ENABLE_GPIO
inout [35:0] GPIO,
`endif
inout nothing
);
// Internal signals
wire [3:0] row, col;
wire [4:0] io_bus; // {valid, keycode}
wire[47:0] HEX;
assign ARDUINO_IO[7:4] = row; // Row scan output
assign col = ARDUINO_IO[3:0]; // Column input
assign ARDUINO_IO[12:8] = io_bus; // Transfer bus
assign valid = io_bus[4];
assign keycode = io_bus[3:0];
// Instantiate Keypad module
Keypad keypad_inst (
.clk(MAX10_CLK1_50),
.rst(~KEY[0]),
.row(row),
.col(col),
.io(io_bus),
.debugled(LEDR[9:5])
);
// Instantiate Combo module
assign HEX= {HEX5, HEX4, HEX3, HEX2, HEX1, HEX0};
Combo combo_inst (
.clk(MAX10_CLK1_50),
.rst(~KEY[0]),
.keycode(io_bus[3:0]),
.valid(io_bus[4]),
.HEX5(HEX5), .HEX4(HEX4), .HEX3(HEX3),
.HEX2(HEX2), .HEX1(HEX1), .HEX0(HEX0),
.debugled(LEDR[4:0])
);
endmodule
QSF: KeyLocker.qsf
# -------------------------------------------------------------------------- #
#
# Copyright (C) 2025 Altera Corporation. All rights reserved.
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and any partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, the Altera Quartus Prime License Agreement,
# the Altera IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Altera and sold by Altera or its authorized distributors. Please
# refer to the Altera Software License Subscription Agreements
# on the Quartus Prime software download page.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 24.1std.0 Build 1077 03/04/2025 SC Lite Edition
# Date created = 09:28:28 十月 12, 2025
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# KeyLocker_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Intel recommends that you do not modify this file. This
# file is updated automatically by the Quartus Prime software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "MAX 10"
set_global_assignment -name DEVICE 10M50DAF484C6GES
set_global_assignment -name TOP_LEVEL_ENTITY DE10_LITE_Golden_Top
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 15.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:45:13 JUNE 17,2016"
set_global_assignment -name LAST_QUARTUS_VERSION "24.1std.0 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 6
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CLK_10
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to MAX10_CLK1_50
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to MAX10_CLK2_50
set_location_assignment PIN_N5 -to ADC_CLK_10
set_location_assignment PIN_P11 -to MAX10_CLK1_50
set_location_assignment PIN_N14 -to MAX10_CLK2_50
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[7]
set_location_assignment PIN_C14 -to HEX0[0]
set_location_assignment PIN_E15 -to HEX0[1]
set_location_assignment PIN_C15 -to HEX0[2]
set_location_assignment PIN_C16 -to HEX0[3]
set_location_assignment PIN_E16 -to HEX0[4]
set_location_assignment PIN_D17 -to HEX0[5]
set_location_assignment PIN_C17 -to HEX0[6]
set_location_assignment PIN_D15 -to HEX0[7]
set_location_assignment PIN_C18 -to HEX1[0]
set_location_assignment PIN_D18 -to HEX1[1]
set_location_assignment PIN_E18 -to HEX1[2]
set_location_assignment PIN_B16 -to HEX1[3]
set_location_assignment PIN_A17 -to HEX1[4]
set_location_assignment PIN_A18 -to HEX1[5]
set_location_assignment PIN_B17 -to HEX1[6]
set_location_assignment PIN_A16 -to HEX1[7]
set_location_assignment PIN_B20 -to HEX2[0]
set_location_assignment PIN_A20 -to HEX2[1]
set_location_assignment PIN_B19 -to HEX2[2]
set_location_assignment PIN_A21 -to HEX2[3]
set_location_assignment PIN_B21 -to HEX2[4]
set_location_assignment PIN_C22 -to HEX2[5]
set_location_assignment PIN_B22 -to HEX2[6]
set_location_assignment PIN_A19 -to HEX2[7]
set_location_assignment PIN_F21 -to HEX3[0]
set_location_assignment PIN_E22 -to HEX3[1]
set_location_assignment PIN_E21 -to HEX3[2]
set_location_assignment PIN_C19 -to HEX3[3]
set_location_assignment PIN_C20 -to HEX3[4]
set_location_assignment PIN_D19 -to HEX3[5]
set_location_assignment PIN_E17 -to HEX3[6]
set_location_assignment PIN_D22 -to HEX3[7]
set_location_assignment PIN_F18 -to HEX4[0]
set_location_assignment PIN_E20 -to HEX4[1]
set_location_assignment PIN_E19 -to HEX4[2]
set_location_assignment PIN_J18 -to HEX4[3]
set_location_assignment PIN_H19 -to HEX4[4]
set_location_assignment PIN_F19 -to HEX4[5]
set_location_assignment PIN_F20 -to HEX4[6]
set_location_assignment PIN_F17 -to HEX4[7]
set_location_assignment PIN_J20 -to HEX5[0]
set_location_assignment PIN_K20 -to HEX5[1]
set_location_assignment PIN_L18 -to HEX5[2]
set_location_assignment PIN_N18 -to HEX5[3]
set_location_assignment PIN_M20 -to HEX5[4]
set_location_assignment PIN_N19 -to HEX5[5]
set_location_assignment PIN_N20 -to HEX5[6]
set_location_assignment PIN_L19 -to HEX5[7]
set_instance_assignment -name IO_STANDARD "3.3 V SCHMITT TRIGGER" -to KEY[0]
set_instance_assignment -name IO_STANDARD "3.3 V SCHMITT TRIGGER" -to KEY[1]
set_location_assignment PIN_B8 -to KEY[0]
set_location_assignment PIN_A7 -to KEY[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[8]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[9]
set_location_assignment PIN_A8 -to LEDR[0]
set_location_assignment PIN_A9 -to LEDR[1]
set_location_assignment PIN_A10 -to LEDR[2]
set_location_assignment PIN_B10 -to LEDR[3]
set_location_assignment PIN_D13 -to LEDR[4]
set_location_assignment PIN_C13 -to LEDR[5]
set_location_assignment PIN_E14 -to LEDR[6]
set_location_assignment PIN_D14 -to LEDR[7]
set_location_assignment PIN_A11 -to LEDR[8]
set_location_assignment PIN_B11 -to LEDR[9]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[8]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[9]
set_location_assignment PIN_C10 -to SW[0]
set_location_assignment PIN_C11 -to SW[1]
set_location_assignment PIN_D12 -to SW[2]
set_location_assignment PIN_C12 -to SW[3]
set_location_assignment PIN_A12 -to SW[4]
set_location_assignment PIN_B12 -to SW[5]
set_location_assignment PIN_A13 -to SW[6]
set_location_assignment PIN_A14 -to SW[7]
set_location_assignment PIN_B14 -to SW[8]
set_location_assignment PIN_F15 -to SW[9]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[8]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[9]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[10]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[11]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[12]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[13]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[14]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[15]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_RESET_N
set_location_assignment PIN_AB5 -to ARDUINO_IO[0]
set_location_assignment PIN_AB6 -to ARDUINO_IO[1]
set_location_assignment PIN_AB7 -to ARDUINO_IO[2]
set_location_assignment PIN_AB8 -to ARDUINO_IO[3]
set_location_assignment PIN_AB9 -to ARDUINO_IO[4]
set_location_assignment PIN_Y10 -to ARDUINO_IO[5]
set_location_assignment PIN_AA11 -to ARDUINO_IO[6]
set_location_assignment PIN_AA12 -to ARDUINO_IO[7]
set_location_assignment PIN_AB17 -to ARDUINO_IO[8]
set_location_assignment PIN_AA17 -to ARDUINO_IO[9]
set_location_assignment PIN_AB19 -to ARDUINO_IO[10]
set_location_assignment PIN_AA19 -to ARDUINO_IO[11]
set_location_assignment PIN_Y19 -to ARDUINO_IO[12]
set_location_assignment PIN_AB20 -to ARDUINO_IO[13]
set_location_assignment PIN_AB21 -to ARDUINO_IO[14]
set_location_assignment PIN_AA20 -to ARDUINO_IO[15]
set_location_assignment PIN_F16 -to ARDUINO_RESET_N
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name VERILOG_FILE DE10_LITE_Golden_Top.v
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name BOARD "MAX 10 DE10 - Lite"
set_global_assignment -name EDA_SIMULATION_TOOL "Questa Intel FPGA (SystemVerilog)"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "SYSTEMVERILOG HDL" -section_id eda_simulation
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to ARDUINO_IO[0]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to ARDUINO_IO[1]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to ARDUINO_IO[2]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to ARDUINO_IO[3]
set_global_assignment -name SYSTEMVERILOG_FILE Keypad.sv
set_global_assignment -name SYSTEMVERILOG_FILE Combo.sv
set_instance_assignment -name RESERVE_PIN AS_INPUT_TRI_STATED -to ARDUINO_IO[3]
set_instance_assignment -name RESERVE_PIN AS_INPUT_TRI_STATED -to ARDUINO_IO[2]
set_instance_assignment -name RESERVE_PIN AS_INPUT_TRI_STATED -to ARDUINO_IO[1]
set_instance_assignment -name RESERVE_PIN AS_INPUT_TRI_STATED -to ARDUINO_IO[0]
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id TopQPF: KeyLocker.qpf
QUARTUS_VERSION = "24.1"
DATE = "09:28:28 十月 12, 2025"
# Revisions
PROJECT_REVISION = "KeyLocker"
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