內容目錄
FSM
flowchart TD
OPEN(OPEN <br> savePW=1 <br> display_sel = 0)
LOCKING(LOCKING <br> savePW=1 <br> display_sel = 0<br> load PSW)
LOCKED(LOCKED<br>saveAT=1<br>display_sel = 1)
UNLOCKING(UNLOCKING<br>saveAT=1<br>display_sel = 1<br> load ATT & test)
S(.) -->|RESET| OPEN --> | ENTER | LOCKING -->| !ENTER | LOCKED
LOCKED -->| ENTER | UNLOCKING -->| !ENTER & MATCH |OPEN
UNLOCKING -->| !ENTER & !MATCH | LOCKED
save.sv
module safe (
input logic CLK50,
input logic [1:0] KEY, // KEY[0]=N_RESET, KEY[1]=N_ENTER (active low)
input logic [9:0] SW,
output logic [9:0] LEDR,
output logic [7:0] HEX5, HEX4, HEX3, HEX2, HEX1, HEX0
);
// 1. DE10-lite key signal Invertion
assign RESET = ~KEY[0]; // active-high reset
assign ENTER = ~KEY[1]; // active-high enter
// 2. Match Logic & LED Hint Info
logic MATCH, PREMATCH;
logic [3:0] HINT;
always_comb begin
MATCH = (ATTEMPT == PASSWORD);
PREMATCH = (SW == PASSWORD);
HINT[3:0] = 0;
for (int i = 0; i < 10; i++)
HINT += (SW[i] ^ PASSWORD[i]);
end
// 3. FSM Integration
logic savePW, saveAT, display_sel;
//***** Choose FSM by remark the other(s)
// fsm_verilog fsm_1 (
fsm_gate fsm_2(
.CLK50 (CLK50),
.RESET (RESET),
.ENTER (ENTER),
.MATCH (MATCH),
.savePW (savePW),
.saveAT (saveAT),
.display_sel (display_sel)
);
// 4. Password / Attempt Registers
logic [9:0] PASSWORD, ATTEMPT;
always_ff @(posedge CLK50) begin
if (RESET) begin
PASSWORD <= 10'b0000000000;
ATTEMPT <= 10'b1111111111;
end else begin
if (savePW) PASSWORD <= SW;
if (saveAT) ATTEMPT <= SW;
end
end
// 5. assign LED for Debug Output
assign LEDR[9] = MATCH;
assign LEDR[8] = PREMATCH;
assign LEDR[7:4] = 4'b00; //unused LEDs, set to 0 or assign anyother debug signals
assign LEDR[3:0] = HINT; // count error bits of ATTEMPT
// 6. HEX Infomation Display
localparam logic [47:0] INFO_OPEN = 48'hF7_C0_8C_86_AB_F7; // "_OPEn_"
localparam logic [47:0] INFO_LOCKED = 48'hC7_C0_C6_89_86_C0; // "LOCHED"
assign {HEX5, HEX4, HEX3, HEX2, HEX1, HEX0} = display_sel ? INFO_LOCKED : INFO_OPEN;
endmodule
fsm_gate.sv
module fsm_gate (
input logic CLK50, // Clock for FF & Sync Reset
input logic RESET, // active-high reset signal
input logic ENTER, // active-high enter signal
input logic MATCH, // attempt == password
output logic savePW, // Moore output: save password
output logic saveAT, // Moore output: save attempt
output logic display_sel // Moore output: display selector
);
// 2-bit state encoding, present state & next state
logic S1, S0, N1, N0;
assign M=MATCH;
assign E=ENTER;
// Sequential logic: state register
always_ff @(posedge CLK50) begin
if (RESET) begin
S1 <= 0; S0 <= 0; //present=0
end else begin
S1 <= N1; S0 <= N0; // present = next
end
end
// Combinational next-state logic
/*
N1N0 |S1S0 E M
-----------------
0 0 | 0 0 0 x
0 0 | 1 1 0 1
0 1 | 0 0 1 x
0 1 | 0 1 1 x
1 0 | 0 1 0 x
1 0 | 1 0 0 x
1 0 | 1 1 0 0
1 1 | 1 1 1 x
1 1 | 1 0 1 x
N1 = (~S1&~S0&E)|(S1&~S0&~E)|(S1&S0&~E&~M)|(S1&S0&E)|(S1&~S0&E);
N0 = (~S1&~S0&E)|(~S1&S1&E)|(S1&S0&E)|(S1&~S0&E);
*/
always_comb begin
N1 = (~S1 & S0 & ~E)|(S1 & ~S0 & ~E)|(S1 & S0 & ~E & ~M)|(S1 & S0 & E)|(S1 & ~S0 & E);
N0 = (~S1 & ~S0 & E)|(~S1 & S1 & E)|(S1 & S0 & E)|(S1 & ~S0 & E);
end
// Moore output logic
always_comb begin
savePW = ~S1; // OPEN or LOCKING
saveAT = S1; // LOCKED or UNLOCKING
display_sel = S1; // 0 for OPEN, 1 otherwise
end
endmodule
fsm_verilog.sv
module fsm_verilog (
input logic CLK50, // Clock for FF & Sync Reset
input logic RESET, // active-high reset signal
input logic ENTER, // active-high enter signal
input logic MATCH, // attempt == password
output logic savePW, // Moore output: save password
output logic saveAT, // Moore output: save attempt
output logic display_sel // Moore output: display selector
);
// 1. State Enumerating
enum int unsigned {
OPEN=0, LOCKING=1, LOCKED=2, UNLOCKING = 3
} present_state, next_state;
// 2. Sequential State Update
always_ff @(posedge CLK50) begin
if (RESET)
present_state <= OPEN;
else
present_state <= next_state;
end
// 3. Combinational Next-State Logic
always_comb begin
// Default outputs
savePW = 0;
saveAT = 0;
display_sel = 0;
case (present_state)
OPEN: begin
next_state = ENTER ? LOCKING : OPEN;
savePW = 1;
display_sel = 0;
end
LOCKING: begin
next_state = ENTER ? LOCKING : LOCKED;
savePW = 1;
display_sel = 0;
end
LOCKED: begin
next_state = ENTER ? UNLOCKING : LOCKED;
saveAT = 1;
display_sel = 1;
end
UNLOCKING: begin
next_state = ENTER ? UNLOCKING :
MATCH ? OPEN : LOCKED;
saveAT = 1;
display_sel = 1;
end
default: begin // prevent failuare if has undefined state
next_state = OPEN;
display_sel = 0;
end
endcase
end
endmodule
save.qsf
# -------------------------------------------------------------------------- #
#
# Copyright (C) 2025 Altera Corporation. All rights reserved.
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and any partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, the Altera Quartus Prime License Agreement,
# the Altera IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Altera and sold by Altera or its authorized distributors. Please
# refer to the Altera Software License Subscription Agreements
# on the Quartus Prime software download page.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 24.1std.0 Build 1077 03/04/2025 SC Lite Edition
# Date created = 21:08:46 September 28, 2025
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# calc_top_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Intel recommends that you do not modify this file. This
# file is updated automatically by the Quartus Prime software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "MAX 10"
set_global_assignment -name DEVICE 10M50DAF484C7G
set_global_assignment -name TOP_LEVEL_ENTITY safe
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 24.1STD.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:08:46 OCTOBER 6, 2025"
set_global_assignment -name LAST_QUARTUS_VERSION "24.1std.0 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
set_global_assignment -name EDA_SIMULATION_TOOL "Questa Intel FPGA (SystemVerilog)"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "SYSTEMVERILOG HDL" -section_id eda_simulation
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLK10_ADC
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLK50
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLK50_2
#set_location_assignment PIN_N5 -to CLK10_ADC
set_location_assignment PIN_P11 -to CLK50
set_location_assignment PIN_N14 -to CLK50_2
# used IO pin assignment (SW、KEY、LEDR、HEX)
# SW[0]–SW[9] IO_STANDARD & PIN assignment
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[8]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[9]
set_location_assignment PIN_C10 -to SW[0]
set_location_assignment PIN_C11 -to SW[1]
set_location_assignment PIN_D12 -to SW[2]
set_location_assignment PIN_C12 -to SW[3]
set_location_assignment PIN_A12 -to SW[4]
set_location_assignment PIN_B12 -to SW[5]
set_location_assignment PIN_A13 -to SW[6]
set_location_assignment PIN_A14 -to SW[7]
set_location_assignment PIN_B14 -to SW[8]
set_location_assignment PIN_F15 -to SW[9]
# KEY[0]–KEY[1] IO_STANDARD & PIN assignment
set_instance_assignment -name IO_STANDARD "3.3 V SCHMITT TRIGGER" -to KEY[0]
set_instance_assignment -name IO_STANDARD "3.3 V SCHMITT TRIGGER" -to KEY[1]
set_location_assignment PIN_B8 -to KEY[0]
set_location_assignment PIN_A7 -to KEY[1]
# LEDR[0]–LEDR[9] IO_STANDARD & PIN assignment
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[8]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[9]
set_location_assignment PIN_A8 -to LEDR[0]
set_location_assignment PIN_A9 -to LEDR[1]
set_location_assignment PIN_A10 -to LEDR[2]
set_location_assignment PIN_B10 -to LEDR[3]
set_location_assignment PIN_D13 -to LEDR[4]
set_location_assignment PIN_C13 -to LEDR[5]
set_location_assignment PIN_E14 -to LEDR[6]
set_location_assignment PIN_D14 -to LEDR[7]
set_location_assignment PIN_A11 -to LEDR[8]
set_location_assignment PIN_B11 -to LEDR[9]
# HEX0–HEX5 IO_STANDARD & PIN assignment
# IO_STANDARD
# HEX0
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[7]
# HEX1
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[7]
# HEX2
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[7]
# HEX3
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[7]
# HEX4
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[7]
# HEX5
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[7]
# PIN assignment
# HEX0
set_location_assignment PIN_C14 -to HEX0[0]
set_location_assignment PIN_E15 -to HEX0[1]
set_location_assignment PIN_C15 -to HEX0[2]
set_location_assignment PIN_C16 -to HEX0[3]
set_location_assignment PIN_E16 -to HEX0[4]
set_location_assignment PIN_D17 -to HEX0[5]
set_location_assignment PIN_C17 -to HEX0[6]
set_location_assignment PIN_D15 -to HEX0[7]
# HEX1
set_location_assignment PIN_C18 -to HEX1[0]
set_location_assignment PIN_D18 -to HEX1[1]
set_location_assignment PIN_E18 -to HEX1[2]
set_location_assignment PIN_B16 -to HEX1[3]
set_location_assignment PIN_A17 -to HEX1[4]
set_location_assignment PIN_A18 -to HEX1[5]
set_location_assignment PIN_B17 -to HEX1[6]
set_location_assignment PIN_A16 -to HEX1[7]
# HEX2
set_location_assignment PIN_B20 -to HEX2[0]
set_location_assignment PIN_A20 -to HEX2[1]
set_location_assignment PIN_B19 -to HEX2[2]
set_location_assignment PIN_A21 -to HEX2[3]
set_location_assignment PIN_B21 -to HEX2[4]
set_location_assignment PIN_C22 -to HEX2[5]
set_location_assignment PIN_B22 -to HEX2[6]
set_location_assignment PIN_A19 -to HEX2[7]
# HEX3
set_location_assignment PIN_F21 -to HEX3[0]
set_location_assignment PIN_E22 -to HEX3[1]
set_location_assignment PIN_E21 -to HEX3[2]
set_location_assignment PIN_C19 -to HEX3[3]
set_location_assignment PIN_C20 -to HEX3[4]
set_location_assignment PIN_D19 -to HEX3[5]
set_location_assignment PIN_E17 -to HEX3[6]
set_location_assignment PIN_D22 -to HEX3[7]
# HEX4
set_location_assignment PIN_F18 -to HEX4[0]
set_location_assignment PIN_E20 -to HEX4[1]
set_location_assignment PIN_E19 -to HEX4[2]
set_location_assignment PIN_J18 -to HEX4[3]
set_location_assignment PIN_H19 -to HEX4[4]
set_location_assignment PIN_F19 -to HEX4[5]
set_location_assignment PIN_F20 -to HEX4[6]
set_location_assignment PIN_F17 -to HEX4[7]
# HEX5
set_location_assignment PIN_J20 -to HEX5[0]
set_location_assignment PIN_K20 -to HEX5[1]
set_location_assignment PIN_L18 -to HEX5[2]
set_location_assignment PIN_N18 -to HEX5[3]
set_location_assignment PIN_M20 -to HEX5[4]
set_location_assignment PIN_N19 -to HEX5[5]
set_location_assignment PIN_N20 -to HEX5[6]
set_location_assignment PIN_L19 -to HEX5[7]
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id TopAdd debouncing circuit on key0/key1
module debounce (
input logic clk,
input logic noisy_in,
output logic clean_out
);
parameter integer COUNT_MAX = 250000; // Adjust for ~5ms at 50MHz
logic [$clog2(COUNT_MAX)-1:0] count;
logic stable_state;
always_ff @(posedge clk) begin
if (noisy_in != stable_state) begin
count <= count + 1;
if (count == COUNT_MAX - 1) begin
stable_state <= noisy_in;
count <= 0;
end
end else begin
count <= 0;
end
end
assign clean_out = stable_state;
endmodule
then rewrite 1st step of save.sv
module safe (
input logic CLK50,
input logic [1:0] KEY, // KEY[0]=N_RESET, KEY[1]=N_ENTER (active low)
input logic [9:0] SW,
output logic [9:0] LEDR,
output logic [7:0] HEX5, HEX4, HEX3, HEX2, HEX1, HEX0
);
// 1. DE10-lite key signal Invertion
logic key0_db, key1_db;
debounce db0 (
.clk (CLK50),
.noisy_in (KEY[0]),
.clean_out (key0_db)
);
debounce db1 (
.clk (CLK50),
.noisy_in (KEY[1]),
.clean_out (key1_db)
);
assign RESET = ~key0_db; // active-high reset
assign ENTER = ~key1_db; // active-high enter
// 2. Match Logic & LED Hint Info
logic MATCH, PREMATCH;
logic [3:0] HINT;
always_comb begin
MATCH = (ATTEMPT == PASSWORD);
PREMATCH = (SW == PASSWORD);
HINT[3:0] = 0;
for (int i = 0; i < 10; i++)
HINT += (SW[i] ^ PASSWORD[i]);
end
// 2. FSM Integration
logic savePW, saveAT, display_sel;
//***** Choose FSM by remark the other(s)
fsm_verilog fsm_1 (
// fsm_gate fsm_2(
.CLK50 (CLK50),
.RESET (RESET),
.ENTER (ENTER),
.MATCH (MATCH),
.savePW (savePW),
.saveAT (saveAT),
.display_sel (display_sel)
);
// 3. Password / Attempt Registers
logic [9:0] PASSWORD, ATTEMPT;
always_ff @(posedge CLK50) begin
if (RESET) begin
PASSWORD <= 10'b0000000000;
ATTEMPT <= 10'b1111111111;
end else begin
if (savePW) PASSWORD <= SW;
if (saveAT) ATTEMPT <= SW;
end
end
// 4. assign LED for Debug Output
assign LEDR[9] = MATCH;
assign LEDR[8] = PREMATCH;
assign LEDR[7:4] = 4'b00; //unused LEDs, set to 0 or assign anyother debug signals
assign LEDR[3:0] = HINT; // count error bits of ATTEMPT
// 5. HEX Infomation Display
localparam logic [47:0] INFO_OPEN = 48'hF7_C0_8C_86_AB_F7; // "_OPEn_"
localparam logic [47:0] INFO_LOCKED = 48'hC7_C0_C6_89_86_C0; // "LOCHED"
assign {HEX5, HEX4, HEX3, HEX2, HEX1, HEX0} = display_sel ? INFO_LOCKED : INFO_OPEN;
endmodule
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