{"id":1098,"date":"2025-10-13T09:06:16","date_gmt":"2025-10-13T01:06:16","guid":{"rendered":"https:\/\/vm1.go2see.me\/?p=1098"},"modified":"2025-10-13T19:12:39","modified_gmt":"2025-10-13T11:12:39","slug":"chatgpt-co-work-for-keypadcombo-safelocker","status":"publish","type":"post","link":"https:\/\/vm1.go2see.me\/?p=1098","title":{"rendered":"ChatGPT co-work sample for KeyPadCombo SafeLocker"},"content":{"rendered":"

\u4eca\u5929<\/p>\n

\u60a8\u8aaa<\/h2>\n
\n

Keypad SafeLocker Keypad SafeLocker has 2 main module Keypad(frontEnd) and Combo(backend), communicated with {valid,keycode} transfer bus io[12:8]. <\/p>\n<\/blockquote>\n

1. Keypad module:<\/h3>\n

4×4 \u9375\u76e4 DE10-Lite<\/p>\n

    \n
  • io[7:4]: row scan with OC, <\/li>\n
  • io[3:0] col read scan value weak pull high. <\/li>\n
  • output key_valid and 4 bit keycode: {valid,keycode} on io[12:8]. key code (in 4bit hex) <\/li>\n
  • scan: R3C3: is 4’h1 R3C2: is 4’h2 R3C1: is 4’h3 R3C0: is 4’hA R2C3: is 4’h4 R2C2: is 4’h5 R2C1: is 4’h6 R2C0: is 4’hB R1C3: is 4’h7 R1C2: is 4’h8 R1C1: is 4’h9 R1C0: is 4’hC R0C3: is 4’hE R0C2: is 4’h0 R0C1: is 4’hF R0C0: is 4’hD <\/li>\n
  • module do rowscan, debouncing, xfer, waitrelease, debouncing with FSM, thus waiting counter can be only 1set with different value. <\/li>\n
  • Each rowscan should wait 1ms for stable, then get key value. <\/li>\n
  • If had key pressed, get it then debouncing for 10ms. <\/li>\n
  • If success get, do xfer for 0.5ms, otherwise scan next. <\/li>\n
  • after xfer, wait key release. need release for 20ms debouncing. <\/li>\n
  • then back to scan next line. debug the {valid,keycode} on LEDR[9:5] <\/li>\n<\/ul>\n

    2. Combo module:<\/h3>\n
      \n
    • receive {valid,keycode} from keypad for password\/attempt entering. <\/li>\n
    • FSM: open – getPSW – locked – getATT, then open if PSW\/ATT match, locked if unmatch. <\/li>\n
    • keycode 4’hE means clear, 4’hF means enter. <\/li>\n
    • 6 digits length for PSW and ATT. <\/li>\n
    • HEX5~HEX0 display shows _OPEn_<\/code> on open state, shows LOCHEO<\/code> on locked state. <\/li>\n
    • on getPSW and getATT state, wait 6 digit number enter. <\/li>\n
    • the getCodeFSM shows current digits have on HEX5~HEX0.\n
        \n
      • if <6 digit, show _ at next enter HEX, follows empty. if >6 digits, keep the last 6 digits on screen. <\/li>\n
      • if 4’hE pressed, delete 1 digit. <\/li>\n
      • if no digits, go back to the open or locked state and show message defined there. <\/li>\n
      • if 4’hF pressed, check entered PSW or ATT length. only 6 digits accept. otherwise show _Err for 1 second, then back to the open or locked state. <\/li>\n<\/ul>\n<\/li>\n
      • debug the current Combo state on LEDR[1:0]<\/li>\n<\/ul>\n

        Copilot \u8aaa<\/h2>\n

        Thanks for sharing the detailed design of your Keypad SafeLocker<\/strong> system! Here’s a breakdown and interpretation of the architecture and behavior, along with some implementation insights to help you debug or refine it:<\/p>\n

        \ud83d\udd10 System Overview<\/h2>\n

        The SafeLocker consists of two main modules:<\/p>\n

        1. Keypad Module (FrontEnd)<\/strong><\/h3>\n

        Handles physical key scanning and debouncing.<\/p>\n

        \ud83d\udd27 Hardware Interface<\/h4>\n
          \n
        • DE10-Lite FPGA Pins<\/strong>:\n
            \n
          • io[7:4]<\/code>: Row scan outputs (Open Collector)<\/li>\n
          • io[3:0]<\/code>: Column inputs (weak pull-up)<\/li>\n
          • io[12:8]<\/code>: Output bus valid, keycode<\/code><\/li>\n<\/ul>\n<\/li>\n<\/ul>\n

            \ud83d\udd22 Key Mapping (Hex Codes)<\/h4>\n\n\n\n\n\n\n\n\n
            Row<\/th>\nC3<\/th>\nC2<\/th>\nC1<\/th>\nC0<\/th>\n<\/tr>\n<\/thead>\n
            R3<\/td>\n1<\/td>\n2<\/td>\n3<\/td>\nA<\/td>\n<\/tr>\n
            R2<\/td>\n4<\/td>\n5<\/td>\n6<\/td>\nB<\/td>\n<\/tr>\n
            R1<\/td>\n7<\/td>\n8<\/td>\n9<\/td>\nC<\/td>\n<\/tr>\n
            R0<\/td>\nE<\/td>\n0<\/td>\nF<\/td>\nD<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

            \u23f1 FSM Timing Behavior<\/h4>\n
              \n
            • Row Scan<\/strong>: Wait 1ms for stable signal.<\/li>\n
            • Key Press Detected<\/strong>:\n
                \n
              • Debounce for 10ms.<\/li>\n
              • If valid, transfer valid, keycode<\/code> for 0.5ms.<\/li>\n
              • If not valid, scan next row.<\/li>\n<\/ul>\n<\/li>\n
              • Post Transfer<\/strong>:\n
                  \n
                • Wait for key release (20ms debounce).<\/li>\n
                • Resume scanning.<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n

                  \ud83e\uddea Debug Output<\/h4>\n
                    \n
                  • valid, keycode<\/code> shown on LEDR[9:5]<\/code>.<\/li>\n<\/ul>\n

                    2. Combo Module (BackEnd)<\/strong><\/h3>\n

                    Handles password entry and access control.<\/p>\n

                    \ud83d\udd01 FSM States<\/h4>\n
                      \n
                    • open<\/code> \u2192 getPSW<\/code> \u2192 locked<\/code> \u2192 getATT<\/code> \u2192 open<\/code> (if match) or locked<\/code> (if not)<\/li>\n<\/ul>\n

                      \ud83d\udd10 Keycode Functions<\/h4>\n
                        \n
                      • 4'hE<\/code>: Clear (delete last digit)<\/li>\n
                      • 4'hF<\/code>: Enter (submit input)<\/li>\n<\/ul>\n

                        \ud83d\udd22 Password\/Attempt Rules<\/h4>\n
                          \n
                        • Must be 6 digits<\/strong>.<\/li>\n
                        • Input shown on HEX5~HEX0<\/code>:\n
                            \n
                          • <6 digits<\/code>: Show _<\/code> at next digit, rest blank.<\/li>\n
                          • >6 digits<\/code>: Keep last 6 digits.<\/li>\n<\/ul>\n<\/li>\n
                          • 4'hE<\/code>: Delete one digit. If empty, return to open<\/code> or locked<\/code>.<\/li>\n
                          • 4'hF<\/code>: Validate length:\n
                              \n
                            • If not 6 digits \u2192 show _Err<\/code> for 1s, then return.<\/li>\n
                            • If 6 digits \u2192 compare with stored PSW\/ATT.<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n

                              \ud83e\uddea Debug Output<\/h4>\n
                                \n
                              • Combo FSM state shown on LEDR[1:0]<\/code>.<\/li>\n<\/ul>\n

                                \ud83e\udde0 Implementation Tips<\/h2>\n

                                FSM Design<\/h3>\n

                                Use a single counter module with parameterized delay values for debounce and timing control. This keeps your design modular and avoids duplication.<\/p>\n

                                Keypad Scan Logic<\/h3>\n
                                  \n
                                • Use a rotating row scan (e.g., one-hot encoding).<\/li>\n
                                • For each row:\n
                                    \n
                                  • Drive low, read columns.<\/li>\n
                                  • If column low \u2192 key press detected.<\/li>\n
                                  • Map row\/col to keycode using lookup table.<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n

                                    Combo FSM<\/h3>\n
                                      \n
                                    • Use a shift register or array to store entered digits.<\/li>\n
                                    • On 4'hE<\/code>, pop last digit.<\/li>\n
                                    • On 4'hF<\/code>, check length and compare.<\/li>\n
                                    • Use a timer FSM to show _Err<\/code> for 1s.<\/li>\n<\/ul>\n

                                      Would you like help writing the Verilog code for either module? Or maybe simulate the FSM behavior to verify transitions?<\/p>\n

                                      \u5728\u9801\u9762\u4e2d\u7de8\u8f2f<\/p>\n

                                      \u60a8\u8aaa<\/h2>\n

                                      creat sv for both block, simulate on same DE10-lite board.<\/p>\n

                                      Copilot \u8aaa<\/h2>\n

                                      Great! Let’s build SystemVerilog modules for both the Keypad<\/strong> and Combo<\/strong> blocks, and simulate them together on the DE10-Lite FPGA<\/strong>. Here’s a complete setup:<\/p>\n

                                      \ud83e\udde9 1. Keypad Module (Keypad.sv<\/code>)<\/h2>\n

                                      This module scans a 4×4 keypad, debounces input, and outputs valid, keycode<\/code> on io[12:8]<\/code>.<\/p>\n

                                      systemverilog<\/p>\n

                                      \u8907\u88fd<\/p>\n

                                      module Keypad (\n    input logic clk, rst,\n    inout logic [7:4] row,     \/\/ Open collector row scan\n    input logic [3:0] col,     \/\/ Column input\n    output logic [12:8] io,    \/\/ {valid, keycode}\n    output logic [9:5] LEDR    \/\/ Debug output\n);\n\n    typedef enum logic [2:0] {\n        SCAN, DEBOUNCE_PRESS, TRANSFER, WAIT_RELEASE, DEBOUNCE_RELEASE\n    } state_t;\n\n    state_t state;\n    logic [3:0] current_row;\n    logic [3:0] keycode;\n    logic valid;\n    logic [15:0] debounce_counter;\n\n    \/\/ Keycode lookup table\n    function logic [3:0] get_keycode(input logic [3:0] r, input logic [3:0] c);\n        case ({r, c})\n            8'h33: return 4'h1; 8'h32: return 4'h2; 8'h31: return 4'h3; 8'h30: return 4'hA;\n            8'h23: return 4'h4; 8'h22: return 4'h5; 8'h21: return 4'h6; 8'h20: return 4'hB;\n            8'h13: return 4'h7; 8'h12: return 4'h8; 8'h11: return 4'h9; 8'h10: return 4'hC;\n            8'h03: return 4'hE; 8'h02: return 4'h0; 8'h01: return 4'hF; 8'h00: return 4'hD;\n            default: return 4'hF;\n        endcase\n    endfunction\n\n    always_ff @(posedge clk or posedge rst) begin\n        if (rst) begin\n            state <= SCAN;\n            current_row <= 4'b1110;\n            debounce_counter <= 0;\n            valid <= 0;\n        end else begin\n            case (state)\n                SCAN: begin\n                    debounce_counter <= debounce_counter + 1;\n                    if (debounce_counter == 1000) begin \/\/ 1ms\n                        if (col != 4'b1111) begin\n                            keycode <= get_keycode(current_row, col);\n                            state <= DEBOUNCE_PRESS;\n                            debounce_counter <= 0;\n                        end else begin\n                            current_row <= {current_row[2:0], current_row[3]};\n                            debounce_counter <= 0;\n                        end\n                    end\n                end\n                DEBOUNCE_PRESS: begin\n                    debounce_counter <= debounce_counter + 1;\n                    if (debounce_counter == 10000) begin \/\/ 10ms\n                        valid <= 1;\n                        state <= TRANSFER;\n                        debounce_counter <= 0;\n                    end\n                end\n                TRANSFER: begin\n                    debounce_counter <= debounce_counter + 1;\n                    if (debounce_counter == 500) begin \/\/ 0.5ms\n                        valid <= 0;\n                        state <= WAIT_RELEASE;\n                        debounce_counter <= 0;\n                    end\n                end\n                WAIT_RELEASE: begin\n                    if (col == 4'b1111) begin\n                        state <= DEBOUNCE_RELEASE;\n                        debounce_counter <= 0;\n                    end\n                end\n                DEBOUNCE_RELEASE: begin\n                    debounce_counter <= debounce_counter + 1;\n                    if (debounce_counter == 20000) begin \/\/ 20ms\n                        state <= SCAN;\n                        debounce_counter <= 0;\n                    end\n                end\n            endcase\n        end\n    end\n\n    assign io = {valid, keycode};\n    assign LEDR[9:5] = io[12:8];\n    assign row = current_row;\n\nendmodule<\/code><\/pre>\n
                                      \ud83d\udd10 2. Combo Module (Combo.sv<\/code>)<\/h2>\n
                                      This module receives valid, keycode<\/code> and manages password entry and access control.<\/p>\n
                                      systemverilog<\/p>\n
                                      \u8907\u88fd<\/p>\n
                                      module Combo (\n    input logic clk, rst,\n    input logic [4:0] keycode,\n    input logic valid,\n    output logic [6:0] HEX[5:0],\n    output logic [1:0] LEDR\n);\n\n    typedef enum logic [1:0] {\n        OPEN, GET_PSW, LOCKED, GET_ATT\n    } state_t;\n\n    state_t state;\n    logic [3:0] psw[5:0], att[5:0], input_buf[5:0];\n    logic [2:0] input_count;\n    logic show_err;\n    logic [15:0] err_timer;\n\n    function logic match(input logic [3:0] a[5:0], input logic [3:0] b[5:0]);\n        for (int i = 0; i < 6; i++) if (a[i] != b[i]) return 0;\n        return 1;\n    endfunction\n\n    always_ff @(posedge clk or posedge rst) begin\n        if (rst) begin\n            state <= OPEN;\n            input_count <= 0;\n            show_err <= 0;\n            err_timer <= 0;\n        end else begin\n            if (valid) begin\n                case (keycode)\n                    4'hE: begin\n                        if (input_count > 0) input_count--;\n                        else state <= (state == GET_PSW) ? OPEN : LOCKED;\n                    end\n                    4'hF: begin\n                        if (input_count == 6) begin\n                            if (state == GET_PSW) begin\n                                for (int i = 0; i < 6; i++) psw[i] <= input_buf[i];\n                                state <= LOCKED;\n                            end else if (state == GET_ATT) begin\n                                for (int i = 0; i < 6; i++) att[i] <= input_buf[i];\n                                state <= match(psw, att) ? OPEN : LOCKED;\n                            end\n                            input_count <= 0;\n                        end else begin\n                            show_err <= 1;\n                            err_timer <= 0;\n                        end\n                    end\n                    default: begin\n                        if (input_count < 6) begin\n                            input_buf[input_count] <= keycode;\n                            input_count++;\n                        end\n                    end\n                endcase\n            end\n\n            if (show_err) begin\n                err_timer <= err_timer + 1;\n                if (err_timer == 50000) begin \/\/ 1s\n                    show_err <= 0;\n                    state <= (state == GET_PSW) ? OPEN : LOCKED;\n                    input_count <= 0;\n                end\n            end\n        end\n    end\n\n    assign LEDR = state;\n\n    \/\/ HEX display logic (simplified)\n    always_comb begin\n        for (int i = 0; i < 6; i++) begin\n            if (show_err) HEX[i] = 7'h79; \/\/ "_Err"\n            else if (state == OPEN) HEX[i] = 7'h3F; \/\/ "O"\n            else if (state == LOCKED) HEX[i] = 7'h38; \/\/ "L"\n            else HEX[i] = (i < input_count) ? input_buf[i] : 7'h00;\n        end\n    end\n\nendmodule<\/code><\/pre>\n
                                      \ud83e\uddea Integration & Simulation<\/h2>\n
                                      To simulate both modules on the DE10-Lite board:<\/p>\n
                                        \n
                                      1. Top Module (<\/strong>SafeLockerTop.sv<\/code>)<\/strong>:\n
                                          \n
                                        • Instantiate both Keypad<\/code> and Combo<\/code>.<\/li>\n
                                        • Connect io[12:8]<\/code> from Keypad to Combo.<\/li>\n
                                        • Map LEDR<\/code>, HEX<\/code>, and io<\/code> to board pins.<\/li>\n<\/ul>\n<\/li>\n
                                        • Constraints File (<\/strong>.qsf<\/code>)<\/strong>:\n
                                            \n
                                          • Assign io[12:0]<\/code>, LEDR[9:0]<\/code>, HEX[5:0]<\/code> to physical pins.<\/li>\n<\/ul>\n<\/li>\n
                                          • Simulation<\/strong>:\n
                                              \n
                                            • Use ModelSim or Quartus simulation tools.<\/li>\n
                                            • Stimulate col<\/code> inputs to simulate key presses.<\/li>\n
                                            • Observe LEDR<\/code> and HEX<\/code> outputs.<\/li>\n<\/ul>\n<\/li>\n<\/ol>\n
                                              Would you like me to generate the top-level module and testbench next?<\/p>\n
                                              \u5728\u9801\u9762\u4e2d\u7de8\u8f2f<\/p>\n
                                              \u60a8\u8aaa<\/h2>\n
                                              top-level module on Quartus<\/p>\n
                                              Copilot \u8aaa<\/h2>\n
                                              Perfect! Here’s a top-level SystemVerilog module<\/strong> that integrates both the Keypad<\/code> and Combo<\/code> modules for your Keypad SafeLocker<\/strong> project on the DE10-Lite<\/strong> board. This module connects the physical I\/O pins, wires up the internal buses, and prepares the design for synthesis in Quartus.<\/p>\n
                                              \ud83e\udde9 SafeLockerTop.sv<\/code><\/h2>\n
                                              systemverilog<\/p>\n
                                              \u8907\u88fd<\/p>\n
                                              module SafeLockerTop (\n    input  logic        CLOCK_50,   \/\/ Main clock\n    input  logic        KEY0,       \/\/ Reset button\n    inout  logic [7:4]  GPIO_ROW,   \/\/ Keypad row scan (OC)\n    input  logic [3:0]  GPIO_COL,   \/\/ Keypad column input\n    output logic [9:0]  LEDR,       \/\/ Debug LEDs\n    output logic [6:0]  HEX0,\n    output logic [6:0]  HEX1,\n    output logic [6:0]  HEX2,\n    output logic [6:0]  HEX3,\n    output logic [6:0]  HEX4,\n    output logic [6:0]  HEX5\n);\n\n    \/\/ Internal signals\n    logic [12:8] io_bus;     \/\/ {valid, keycode}\n    logic [4:0] keycode;\n    logic       valid;\n\n    \/\/ Instantiate Keypad module\n    Keypad keypad_inst (\n        .clk(CLOCK_50),\n        .rst(~KEY0),\n        .row(GPIO_ROW),\n        .col(GPIO_COL),\n        .io(io_bus),\n        .LEDR(LEDR[9:5])\n    );\n\n    assign valid    = io_bus[12];\n    assign keycode  = io_bus[11:8];\n\n    \/\/ Instantiate Combo module\n    Combo combo_inst (\n        .clk(CLOCK_50),\n        .rst(~KEY0),\n        .keycode(keycode),\n        .valid(valid),\n        .HEX({HEX5, HEX4, HEX3, HEX2, HEX1, HEX0}),\n        .LEDR(LEDR[1:0])\n    );\n\nendmodule<\/code><\/pre>\n
                                              \ud83d\udee0 Quartus Setup Tips<\/h2>\n
                                              1. Project Creation<\/strong><\/h3>\n
                                                \n
                                              • Create a new Quartus project named SafeLocker<\/code>.<\/li>\n
                                              • Add SafeLockerTop.sv<\/code>, Keypad.sv<\/code>, and Combo.sv<\/code> to the project.<\/li>\n<\/ul>\n
                                                2. Pin Assignments<\/strong><\/h3>\n
                                                Use the Pin Planner<\/strong> or .qsf<\/code> file to assign physical pins:<\/p>\n\n\n\n\n\n\n\n\n\n\n
                                                Signal<\/th>\nDE10-Lite Pin Name<\/th>\nNotes<\/th>\n<\/tr>\n<\/thead>\n
                                                CLOCK_50<\/code><\/td>\nPIN_A9<\/td>\n50 MHz clock<\/td>\n<\/tr>\n
                                                KEY0<\/code><\/td>\nPIN_N2<\/td>\nPush button (active low)<\/td>\n<\/tr>\n
                                                GPIO_ROW[7:4]<\/code><\/td>\nPINs (e.g., D13, E13, F13, G13)<\/td>\nRow scan pins<\/td>\n<\/tr>\n
                                                GPIO_COL[3:0]<\/code><\/td>\nPINs (e.g., H13, J13, K13, L13)<\/td>\nColumn input pins<\/td>\n<\/tr>\n
                                                LEDR[9:0]<\/code><\/td>\nPINs (e.g., M1\u2013M10)<\/td>\nDebug LEDs<\/td>\n<\/tr>\n
                                                HEX[5:0]<\/code><\/td>\nPINs for 7-seg displays<\/td>\nAssign accordingly<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n
                                                3. Compilation<\/strong><\/h3>\n
                                                  \n
                                                • Compile the project.<\/li>\n
                                                • Check for timing violations and resolve if needed.<\/li>\n
                                                • Use the TimeQuest Timing Analyzer<\/strong> to verify debounce delays.<\/li>\n<\/ul>\n
                                                  4. Simulation (Optional)<\/strong><\/h3>\n
                                                    \n
                                                  • Use ModelSim to simulate SafeLockerTop<\/code>.<\/li>\n
                                                  • Stimulate GPIO_COL<\/code> to emulate key presses.<\/li>\n
                                                  • Observe LEDR<\/code> and HEX<\/code> outputs.<\/li>\n<\/ul>\n
                                                    Would you like help writing the .qsf<\/code> pin assignment file or a testbench for simulation?<\/p>\n
                                                    \u5728\u9801\u9762\u4e2d\u7de8\u8f2f<\/p>\n
                                                    \u60a8\u8aaa<\/h2>\n
                                                    50MHz clock<\/p>\n
                                                    Copilot \u8aaa<\/h2>\n
                                                    The 50 MHz clock<\/strong> on the DE10-Lite board<\/strong> is your main timing source, and it’s perfect for driving FSMs and debounce counters in your SafeLocker design.<\/p>\n
                                                    To use it effectively in your SystemVerilog modules:<\/p>\n
                                                    \ud83d\udd52 Timing Reference<\/h2>\n
                                                      \n
                                                    • Clock Frequency<\/strong>: 50 MHz<\/li>\n
                                                    • Clock Period<\/strong>:<\/li>\n<\/ul>\n
                                                      T=150\u00d7106=20 ns<\/p>\n
                                                      So every tick of the clock is 20 nanoseconds.<\/p>\n
                                                      \u23f1 Delay Calculations<\/h2>\n
                                                      To implement delays like 1ms, 10ms, etc., you\u2019ll need counters:<\/p>\n\n\n\n\n\n\n\n\n\n
                                                      Delay<\/th>\nClock Cycles Needed<\/th>\nCounter Width<\/th>\n<\/tr>\n<\/thead>\n
                                                      0.5 ms<\/td>\n25,000 cycles<\/td>\n15 bits<\/td>\n<\/tr>\n
                                                      1 ms<\/td>\n50,000 cycles<\/td>\n16 bits<\/td>\n<\/tr>\n
                                                      10 ms<\/td>\n500,000 cycles<\/td>\n19 bits<\/td>\n<\/tr>\n
                                                      20 ms<\/td>\n1,000,000 cycles<\/td>\n20 bits<\/td>\n<\/tr>\n
                                                      1 sec<\/td>\n50,000,000 cycles<\/td>\n26 bits<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n
                                                      Use these values to size your debounce and wait counters in the FSMs.<\/p>\n
                                                      \ud83e\udde0 Example Counter Snippet<\/h2>\n
                                                      logic [19:0] counter;\nalways_ff @(posedge clk or posedge rst) begin\n    if (rst)\n        counter <= 0;\n    else if (counter < 500_000) \/\/ 10ms\n        counter <= counter + 1;\n    else\n        counter <= 0; \/\/ Done waiting\nend<\/code><\/pre>\n
                                                      If you\u2019d like, I can help you refactor your FSMs to use a shared timing module or generate a parameterized delay module for reuse. Want to go that route?<\/p>\n
                                                      .<\/p>\n
                                                      .<\/p>\n
                                                      .<\/p>\n
                                                      .<\/p>\n
                                                      \n
                                                      ==> worked keypad.sv<\/code> :<\/h2>\n
                                                      module Keypad (\n    input logic clk, rst,\n    inout logic [7:4] row,     \/\/ Open collector row scan\n    input logic [3:0] col,     \/\/ Column input\n    output logic [4:0] io,    \/\/ {valid, keycode}\n    output logic [9:5] debugled    \/\/ Debug led output\n);\n\n    typedef enum logic [2:0] {\n        SCAN, DEBOUNCE_PRESS, TRANSFER, WAIT_RELEASE, RESTART\n    } state_t;\n\n    state_t state;\n    logic [3:0] current_row;\n    logic [3:0] keycode;\n    logic valid;\n\n    \/\/ large delay\/debounce counter for all state. in 50MHz system, 1ms take 50,000 cycles \n    \/\/ since designed for 20ms max. => take 1,000,000 cycles, need 20 bits...\n    \/\/ just one counter be needed in this FSM sequence flow...\n    logic [19:0] debounce_counter; \n\n    \/\/ Keycode lookup function\n    function logic [3:0] get_keycode(input logic [3:0] r, input logic [3:0] c);\n        case ({r, c})\n            8'b0111_0111: return 4'h1; 8'b0111_1011: return 4'h2; 8'b0111_1101: return 4'h3; 8'b0111_1110: return 4'hA;\n            8'b1011_0111: return 4'h4; 8'b1011_1011: return 4'h5; 8'b1011_1101: return 4'h6; 8'b1011_1110: return 4'hB;\n            8'b1101_0111: return 4'h7; 8'b1101_1011: return 4'h8; 8'b1101_1101: return 4'h9; 8'b1101_1110: return 4'hC;\n            8'b1110_0111: return 4'hE; 8'b1110_1011: return 4'h0; 8'b1110_1101: return 4'hF; 8'b1110_1110: return 4'hD;\n            default: return 4'hA; \/\/ err? give a non-noise signal for test...\n        endcase\n    endfunction\n\n    \/\/ FSM to get and transfer key value\n    always_ff @(posedge clk or posedge rst) begin\n        if (rst) begin\n            state <= RESTART; \/\/ do samething as restart FSM...\n        end else begin\n            case (state)\n                SCAN: begin \/\/ add 1ms row signal wait, 4 rows need 4ms in one scan loop...\n                    debounce_counter <= debounce_counter + 1;\n                    \/\/ wait 1ms for scan signal stable (L\/R\/C issue for long wire)\n                    if (debounce_counter == 1*50000) begin \/\/ 1ms\n                        if (col != 4'b1111) begin \/\/ key be scaned?\n                            keycode <= get_keycode(current_row, col); \n                            state <= DEBOUNCE_PRESS; \/\/ not valid before measure...\n                            debounce_counter <= 0;\n                        end else begin \/\/ change to next scan pin (through current_row bit rotate)\n                            current_row <= {current_row[2:0], current_row[3]};\n                            debounce_counter <= 0;\n                        end\n                    end\n                end\n                DEBOUNCE_PRESS: begin \/\/ mechanically bouncing issue, might longer if meet bad keypad...\n                    debounce_counter <= debounce_counter + 1;\n                    if (debounce_counter == 10*50000) begin \/\/ 10ms\n                        \/\/ 10ms debounce check. if fail, do next scan, else do keycode xfer.\n                        state <= (keycode==get_keycode(current_row, col))? TRANSFER:WAIT_RELEASE;\n                        debounce_counter <= 0;\n                    end\n                end\n                TRANSFER: begin \/\/ doing > > 3 cycle data transfer.\n                    debounce_counter <= debounce_counter + 1;\n                    valid <= 1; \/\/ xfer keycode, keep signal during transfer cycles.\n                    if (debounce_counter == 50000\/2) begin \/\/ 0.5ms > > 3 cycle in spec., but longer is better for slow receiver\n                        state <= WAIT_RELEASE;\n                        debounce_counter <= 0;\n                    end\n                end\n                WAIT_RELEASE: begin \/\/ after transfer or error key signal, wait the key up\n                    debounce_counter <= debounce_counter + 1;\n                    if (col == 4'b1111) valid <= 0; \/\/ had released? invalid transfer signal\n                    else  debounce_counter <= 0; \/\/ any noise in debouncing? keep waitting...\n                    if (debounce_counter == 20*50000) begin \/\/ 20ms no key ==> done, no next scan...\n                        state <= SCAN;\n                        debounce_counter <= 0;\n                    end\n                end\n                RESTART: begin \/\/ initialize and start scan\n                    state <= SCAN;\n                    current_row <= 4'b1110; \/\/ scan row initialize\n                    debounce_counter <= 0;  \/\/ delay\/debug counter reset\n                    valid <= 0;\n                    keycode <=0;\n                end\n                default: state <= RESTART; \/\/ take care all of the illeagle states in FSM!!\n            endcase\n        end\n    end\n\n    assign io = {valid, keycode}; \/\/ signal to other module\/boards...\n    assign debugled = io;\n    assign row = current_row;\n\nendmodule<\/code><\/pre>\n
                                                      ==> worked Combo.sv<\/code> :<\/h2>\n
                                                      module Combo (\n    input  logic clk, rst,\n    input  logic [3:0] keycode,\n    input  logic       valid,\n    output logic [7:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5,\n    output logic [1:0] debugled\n);\n\n    typedef enum logic [1:0] {\n        OPEN, GET_PSW, LOCKED, GET_ATT\n    } state_t;\n    state_t state;\n\n    logic [3:0] psw[5:0], att[5:0], input_buf[5:0];\n    logic [2:0] input_count;\n    logic show_err;\n    logic [25:0] err_timer;\n    logic wait_release;\n\n    function logic match(input logic [3:0] a[5:0], input logic [3:0] b[5:0]);\n        for (int i = 0; i < 6; i++) if (a[i] != b[i]) return 0;\n        return 1;\n    endfunction\n\n    function logic [7:0] seg_decode(input logic [3:0] val);\n        case (val)\n            4'h0: seg_decode = 8'b11000000;\n            4'h1: seg_decode = 8'b11111001;\n            4'h2: seg_decode = 8'b10100100;\n            4'h3: seg_decode = 8'b10110000;\n            4'h4: seg_decode = 8'b10011001;\n            4'h5: seg_decode = 8'b10010010;\n            4'h6: seg_decode = 8'b10000010;\n            4'h7: seg_decode = 8'b11111000;\n            4'h8: seg_decode = 8'b10000000;\n            4'h9: seg_decode = 8'b10010000;\n            4'hA: seg_decode = 8'b10001000;\n            4'hB: seg_decode = 8'b10000011;\n            4'hC: seg_decode = 8'b11000110;\n            4'hD: seg_decode = 8'b10100001;\n            4'hE: seg_decode = 8'b10000110;\n            4'hF: seg_decode = 8'b10001110;\n            default: seg_decode = 8'b11111111;\n        endcase\n    endfunction\n\n    function logic [7:0] char_decode(input byte ch);\n        case (ch)\n            "_": char_decode = 8'b11110111;\n            "O": char_decode = 8'b11000000;\n            "P": char_decode = 8'b10001100;\n            "E": char_decode = 8'b10000110;\n            "N": char_decode = 8'b10101011;\n            "L": char_decode = 8'b11000111;\n            "C": char_decode = 8'b11000110;\n            "H": char_decode = 8'b10001001;\n            "r": char_decode = 8'b10101111;\n            "D": char_decode = 8'b10100001;\n            default: char_decode = 8'b11111111;\n        endcase\n    endfunction\n\n    always_ff @(posedge clk or posedge rst) begin\n        if (rst) begin\n            state <= OPEN;\n            input_count <= 0;\n            show_err <= 0;\n            err_timer <= 0;\n            wait_release <= 0;\n        end else begin\n            case (state)\n                OPEN: begin\n                    if (valid && !wait_release) begin\n                        state <= GET_PSW;\n                        wait_release <= 1;\n                    end else if (!valid) begin\n                        wait_release <= 0;\n                    end\n                end\n                LOCKED: begin\n                    if (valid && !wait_release) begin\n                        state <= GET_ATT;\n                        wait_release <= 1;\n                    end else if (!valid) begin\n                        wait_release <= 0;\n                    end\n                end\n                GET_PSW, GET_ATT: begin\n                    if (show_err) begin\n                        err_timer <= err_timer + 1;\n                        if (err_timer == 50_000_000) begin\n                            show_err <= 0;\n                            input_count <= 0;\n                            state <= (state == GET_PSW) ? OPEN : LOCKED;\n                        end\n                    end else if (valid && !wait_release) begin\n                        wait_release <= 1;\n                        if (keycode == 4'hE) begin\n                            if (input_count > 0) begin\n                                input_count <= input_count - 1;\n                                input_buf[input_count - 1] <= 4'hF;\n                            end else begin\n                                state <= (state == GET_PSW) ? OPEN : LOCKED;\n                            end\n                        end else if (keycode == 4'hF) begin\n                            if (input_count == 6) begin\n                                if (state == GET_PSW) begin\n                                    for (int i = 0; i < 6; i++) psw[i] <= input_buf[i];\n                                    state <= LOCKED;\n                                end else begin\n                                    for (int i = 0; i < 6; i++) att[i] <= input_buf[i];\n                                    state <= match(psw, att) ? OPEN : LOCKED;\n                                end\n                                input_count <= 0;\n                            end else begin\n                                show_err <= 1;\n                                err_timer <= 0;\n                            end\n                        end else begin\n                            if (input_count < 6) begin\n                                input_buf[input_count] <= keycode;\n                                input_count <= input_count + 1;\n                            end else begin\n                                for (int i = 0; i < 5; i++) input_buf[i] <= input_buf[i+1];\n                                input_buf[5] <= keycode;\n                            end\n                        end\n                    end else if (!valid) begin\n                        wait_release <= 0;\n                    end\n                end\n            endcase\n        end\n    end\n\n    assign LEDR = state;\n\n    always_comb begin\n        if (show_err) begin\n            HEX5 = char_decode("_");\n            HEX4 = char_decode("E");\n            HEX3 = char_decode("r");\n            HEX2 = char_decode("r");\n            HEX1 = char_decode("_");\n            HEX0 = char_decode(" ");\n        end else case (state)\n            OPEN: begin\n                HEX5 = char_decode("_");\n                HEX4 = char_decode("O");\n                HEX3 = char_decode("P");\n                HEX2 = char_decode("E");\n                HEX1 = char_decode("N");\n                HEX0 = char_decode("_");\n            end\n            LOCKED: begin\n                HEX5 = char_decode("L");\n                HEX4 = char_decode("O");\n                HEX3 = char_decode("C");\n                HEX2 = char_decode("H");\n                HEX1 = char_decode("E");\n                HEX0 = char_decode("D");\n            end\n            GET_PSW, GET_ATT: begin\n                HEX5 = (input_count > 0) ? seg_decode(input_buf[0]) : (input_count == 0) ? char_decode("_") : 8'hFF;\n                HEX4 = (input_count > 1) ? seg_decode(input_buf[1]) : (input_count == 1) ? char_decode("_") : 8'hFF;\n                HEX3 = (input_count > 2) ? seg_decode(input_buf[2]) : (input_count == 2) ? char_decode("_") : 8'hFF;\n                HEX2 = (input_count > 3) ? seg_decode(input_buf[3]) : (input_count == 3) ? char_decode("_") : 8'hFF;\n                HEX1 = (input_count > 4) ? seg_decode(input_buf[4]) : (input_count == 4) ? char_decode("_") : 8'hFF;\n                HEX0 = (input_count > 5) ? seg_decode(input_buf[5]) : (input_count == 5) ? char_decode("_") : 8'hFF;\n            end\n        endcase\n    end\n\nendmodule\n<\/code><\/pre>\n
                                                      Top: DE10_LITE_Golden_Top.v<\/h2>\n
                                                      \/\/ ============================================================================\n\/\/   Ver  :| Author                 :| Mod. Date :| Changes Made:\n\/\/   V1.1 :| Alexandra Du           :| 06\/01\/2016:| Added Verilog file\n\/\/ ============================================================================\n\n\/\/=======================================================\n\/\/  This code is generated by Terasic System Builder\n\/\/=======================================================\n\n`define ENABLE_ADC_CLOCK\n`define ENABLE_CLOCK1\n`define ENABLE_CLOCK2\n`define ENABLE_SDRAM\n`define ENABLE_HEX0\n`define ENABLE_HEX1\n`define ENABLE_HEX2\n`define ENABLE_HEX3\n`define ENABLE_HEX4\n`define ENABLE_HEX5\n`define ENABLE_KEY\n`define ENABLE_LED\n`define ENABLE_SW\n`define ENABLE_VGA\n`define ENABLE_ACCELEROMETER\n`define ENABLE_ARDUINO\n`define ENABLE_GPIO\n\nmodule DE10_LITE_Golden_Top(\n\n    \/\/\/\/\/\/\/\/\/\/\/\/ ADC CLOCK: 3.3-V LVTTL \/\/\/\/\/\/\/\/\/\/\n`ifdef ENABLE_ADC_CLOCK\n    input                       ADC_CLK_10,\n`endif\n    \/\/\/\/\/\/\/\/\/\/\/\/ CLOCK 1: 3.3-V LVTTL \/\/\/\/\/\/\/\/\/\/\n`ifdef ENABLE_CLOCK1\n    input                       MAX10_CLK1_50,\n`endif\n    \/\/\/\/\/\/\/\/\/\/\/\/ CLOCK 2: 3.3-V LVTTL \/\/\/\/\/\/\/\/\/\/\n`ifdef ENABLE_CLOCK2\n    input                       MAX10_CLK2_50,\n`endif\n\n    \/\/\/\/\/\/\/\/\/\/\/\/ SDRAM: 3.3-V LVTTL \/\/\/\/\/\/\/\/\/\/\n`ifdef ENABLE_SDRAM\n    output          [12:0]      DRAM_ADDR,\n    output           [1:0]      DRAM_BA,\n    output                      DRAM_CAS_N,\n    output                      DRAM_CKE,\n    output                      DRAM_CLK,\n    output                      DRAM_CS_N,\n    inout           [15:0]      DRAM_DQ,\n    output                      DRAM_LDQM,\n    output                      DRAM_RAS_N,\n    output                      DRAM_UDQM,\n    output                      DRAM_WE_N,\n`endif\n\n    \/\/\/\/\/\/\/\/\/\/\/\/ SEG7: 3.3-V LVTTL \/\/\/\/\/\/\/\/\/\/\n`ifdef ENABLE_HEX0\n    output           [7:0]      HEX0,\n`endif\n`ifdef ENABLE_HEX1\n    output           [7:0]      HEX1,\n`endif\n`ifdef ENABLE_HEX2\n    output           [7:0]      HEX2,\n`endif\n`ifdef ENABLE_HEX3\n    output           [7:0]      HEX3,\n`endif\n`ifdef ENABLE_HEX4\n    output           [7:0]      HEX4,\n`endif\n`ifdef ENABLE_HEX5\n    output           [7:0]      HEX5,\n`endif\n\n    \/\/\/\/\/\/\/\/\/\/\/\/ KEY: 3.3 V SCHMITT TRIGGER \/\/\/\/\/\/\/\/\/\/\n`ifdef ENABLE_KEY\n    input            [1:0]      KEY,\n`endif\n\n    \/\/\/\/\/\/\/\/\/\/\/\/ LED: 3.3-V LVTTL \/\/\/\/\/\/\/\/\/\/\n`ifdef ENABLE_LED\n    output           [9:0]      LEDR,\n`endif\n\n    \/\/\/\/\/\/\/\/\/\/\/\/ SW: 3.3-V LVTTL \/\/\/\/\/\/\/\/\/\/\n`ifdef ENABLE_SW\n    input            [9:0]      SW,\n`endif\n\n    \/\/\/\/\/\/\/\/\/\/\/\/ VGA: 3.3-V LVTTL \/\/\/\/\/\/\/\/\/\/\n`ifdef ENABLE_VGA\n    output           [3:0]      VGA_B,\n    output           [3:0]      VGA_G,\n    output                      VGA_HS,\n    output           [3:0]      VGA_R,\n    output                      VGA_VS,\n`endif\n\n    \/\/\/\/\/\/\/\/\/\/\/\/ Accelerometer: 3.3-V LVTTL \/\/\/\/\/\/\/\/\/\/\n`ifdef ENABLE_ACCELEROMETER\n    output                      GSENSOR_CS_N,\n    input            [2:1]      GSENSOR_INT,\n    output                      GSENSOR_SCLK,\n    inout                       GSENSOR_SDI,\n    inout                       GSENSOR_SDO,\n`endif\n\n    \/\/\/\/\/\/\/\/\/\/\/\/ Arduino: 3.3-V LVTTL \/\/\/\/\/\/\/\/\/\/\n`ifdef ENABLE_ARDUINO\n    inout           [15:0]      ARDUINO_IO,\n    inout                       ARDUINO_RESET_N,\n`endif\n\n    \/\/\/\/\/\/\/\/\/\/\/\/ GPIO, GPIO connect to GPIO Default: 3.3-V LVTTL \/\/\/\/\/\/\/\/\/\/\n`ifdef ENABLE_GPIO\n    inout           [35:0]      GPIO,\n`endif\ninout nothing\n);\n\n    \/\/ Internal signals\n    wire [3:0] row, col;\n    wire [4:0] io_bus; \/\/ {valid, keycode}\n     wire[47:0] HEX;\n\n    assign ARDUINO_IO[7:4] = row;       \/\/ Row scan output\n    assign col = ARDUINO_IO[3:0];       \/\/ Column input\n    assign ARDUINO_IO[12:8] = io_bus;   \/\/ Transfer bus\n\n     assign valid    = io_bus[4];\n    assign keycode  = io_bus[3:0];\n\n    \/\/ Instantiate Keypad module\n    Keypad keypad_inst (\n        .clk(MAX10_CLK1_50),\n        .rst(~KEY[0]),\n        .row(row),\n        .col(col),\n        .io(io_bus),\n        .debugled(LEDR[9:5])\n    );\n\n    \/\/ Instantiate Combo module\n\n    assign HEX= {HEX5, HEX4, HEX3, HEX2, HEX1, HEX0};\n    Combo combo_inst (\n        .clk(MAX10_CLK1_50),\n        .rst(~KEY[0]),\n        .keycode(io_bus[3:0]),\n        .valid(io_bus[4]),\n        .HEX5(HEX5), .HEX4(HEX4), .HEX3(HEX3),\n          .HEX2(HEX2), .HEX1(HEX1), .HEX0(HEX0),\n        .debugled(LEDR[4:0])\n    );\n\nendmodule\n<\/code><\/pre>\n
                                                      QSF: KeyLocker.qsf<\/h3>\n
                                                      # -------------------------------------------------------------------------- #\n#\n# Copyright (C) 2025  Altera Corporation. All rights reserved.\n# Your use of Altera Corporation's design tools, logic functions \n# and other software and tools, and any partner logic \n# functions, and any output files from any of the foregoing \n# (including device programming or simulation files), and any \n# associated documentation or information are expressly subject \n# to the terms and conditions of the Altera Program License \n# Subscription Agreement, the Altera Quartus Prime License Agreement,\n# the Altera IP License Agreement, or other applicable license\n# agreement, including, without limitation, that your use is for\n# the sole purpose of programming logic devices manufactured by\n# Altera and sold by Altera or its authorized distributors.  Please\n# refer to the Altera Software License Subscription Agreements \n# on the Quartus Prime software download page.\n#\n# -------------------------------------------------------------------------- #\n#\n# Quartus Prime\n# Version 24.1std.0 Build 1077 03\/04\/2025 SC Lite Edition\n# Date created = 09:28:28  \u5341\u6708 12, 2025\n#\n# -------------------------------------------------------------------------- #\n#\n# Notes:\n#\n# 1) The default values for assignments are stored in the file:\n#       KeyLocker_assignment_defaults.qdf\n#    If this file doesn't exist, see file:\n#       assignment_defaults.qdf\n#\n# 2) Intel recommends that you do not modify this file. This\n#    file is updated automatically by the Quartus Prime software\n#    and any changes you make may be lost or overwritten.\n#\n# -------------------------------------------------------------------------- #\n\nset_global_assignment -name FAMILY "MAX 10"\nset_global_assignment -name DEVICE 10M50DAF484C6GES\nset_global_assignment -name TOP_LEVEL_ENTITY DE10_LITE_Golden_Top\nset_global_assignment -name ORIGINAL_QUARTUS_VERSION 15.1.0\nset_global_assignment -name PROJECT_CREATION_TIME_DATE "17:45:13 JUNE 17,2016"\nset_global_assignment -name LAST_QUARTUS_VERSION "24.1std.0 Lite Edition"\nset_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files\nset_global_assignment -name DEVICE_FILTER_PACKAGE FBGA\nset_global_assignment -name DEVICE_FILTER_PIN_COUNT 484\nset_global_assignment -name DEVICE_FILTER_SPEED_GRADE 6\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CLK_10\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to MAX10_CLK1_50\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to MAX10_CLK2_50\nset_location_assignment PIN_N5 -to ADC_CLK_10\nset_location_assignment PIN_P11 -to MAX10_CLK1_50\nset_location_assignment PIN_N14 -to MAX10_CLK2_50\n\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[0]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[1]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[2]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[3]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[4]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[5]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[6]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[7]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[0]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[1]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[2]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[3]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[4]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[5]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[6]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[7]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[0]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[1]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[2]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[3]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[4]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[5]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[6]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[7]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[0]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[1]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[2]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[3]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[4]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[5]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[6]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[7]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[0]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[1]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[2]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[3]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[4]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[5]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[6]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[7]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[0]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[1]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[2]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[3]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[4]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[5]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[6]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[7]\nset_location_assignment PIN_C14 -to HEX0[0]\nset_location_assignment PIN_E15 -to HEX0[1]\nset_location_assignment PIN_C15 -to HEX0[2]\nset_location_assignment PIN_C16 -to HEX0[3]\nset_location_assignment PIN_E16 -to HEX0[4]\nset_location_assignment PIN_D17 -to HEX0[5]\nset_location_assignment PIN_C17 -to HEX0[6]\nset_location_assignment PIN_D15 -to HEX0[7]\nset_location_assignment PIN_C18 -to HEX1[0]\nset_location_assignment PIN_D18 -to HEX1[1]\nset_location_assignment PIN_E18 -to HEX1[2]\nset_location_assignment PIN_B16 -to HEX1[3]\nset_location_assignment PIN_A17 -to HEX1[4]\nset_location_assignment PIN_A18 -to HEX1[5]\nset_location_assignment PIN_B17 -to HEX1[6]\nset_location_assignment PIN_A16 -to HEX1[7]\nset_location_assignment PIN_B20 -to HEX2[0]\nset_location_assignment PIN_A20 -to HEX2[1]\nset_location_assignment PIN_B19 -to HEX2[2]\nset_location_assignment PIN_A21 -to HEX2[3]\nset_location_assignment PIN_B21 -to HEX2[4]\nset_location_assignment PIN_C22 -to HEX2[5]\nset_location_assignment PIN_B22 -to HEX2[6]\nset_location_assignment PIN_A19 -to HEX2[7]\nset_location_assignment PIN_F21 -to HEX3[0]\nset_location_assignment PIN_E22 -to HEX3[1]\nset_location_assignment PIN_E21 -to HEX3[2]\nset_location_assignment PIN_C19 -to HEX3[3]\nset_location_assignment PIN_C20 -to HEX3[4]\nset_location_assignment PIN_D19 -to HEX3[5]\nset_location_assignment PIN_E17 -to HEX3[6]\nset_location_assignment PIN_D22 -to HEX3[7]\nset_location_assignment PIN_F18 -to HEX4[0]\nset_location_assignment PIN_E20 -to HEX4[1]\nset_location_assignment PIN_E19 -to HEX4[2]\nset_location_assignment PIN_J18 -to HEX4[3]\nset_location_assignment PIN_H19 -to HEX4[4]\nset_location_assignment PIN_F19 -to HEX4[5]\nset_location_assignment PIN_F20 -to HEX4[6]\nset_location_assignment PIN_F17 -to HEX4[7]\nset_location_assignment PIN_J20 -to HEX5[0]\nset_location_assignment PIN_K20 -to HEX5[1]\nset_location_assignment PIN_L18 -to HEX5[2]\nset_location_assignment PIN_N18 -to HEX5[3]\nset_location_assignment PIN_M20 -to HEX5[4]\nset_location_assignment PIN_N19 -to HEX5[5]\nset_location_assignment PIN_N20 -to HEX5[6]\nset_location_assignment PIN_L19 -to HEX5[7]\nset_instance_assignment -name IO_STANDARD "3.3 V SCHMITT TRIGGER" -to KEY[0]\nset_instance_assignment -name IO_STANDARD "3.3 V SCHMITT TRIGGER" -to KEY[1]\nset_location_assignment PIN_B8 -to KEY[0]\nset_location_assignment PIN_A7 -to KEY[1]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[0]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[1]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[2]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[3]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[4]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[5]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[6]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[7]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[8]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[9]\nset_location_assignment PIN_A8 -to LEDR[0]\nset_location_assignment PIN_A9 -to LEDR[1]\nset_location_assignment PIN_A10 -to LEDR[2]\nset_location_assignment PIN_B10 -to LEDR[3]\nset_location_assignment PIN_D13 -to LEDR[4]\nset_location_assignment PIN_C13 -to LEDR[5]\nset_location_assignment PIN_E14 -to LEDR[6]\nset_location_assignment PIN_D14 -to LEDR[7]\nset_location_assignment PIN_A11 -to LEDR[8]\nset_location_assignment PIN_B11 -to LEDR[9]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[4]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[5]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[6]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[7]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[8]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[9]\nset_location_assignment PIN_C10 -to SW[0]\nset_location_assignment PIN_C11 -to SW[1]\nset_location_assignment PIN_D12 -to SW[2]\nset_location_assignment PIN_C12 -to SW[3]\nset_location_assignment PIN_A12 -to SW[4]\nset_location_assignment PIN_B12 -to SW[5]\nset_location_assignment PIN_A13 -to SW[6]\nset_location_assignment PIN_A14 -to SW[7]\nset_location_assignment PIN_B14 -to SW[8]\nset_location_assignment PIN_F15 -to SW[9]\n\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[0]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[1]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[2]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[3]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[4]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[5]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[6]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[7]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[8]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[9]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[10]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[11]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[12]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[13]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[14]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[15]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_RESET_N\nset_location_assignment PIN_AB5 -to ARDUINO_IO[0]\nset_location_assignment PIN_AB6 -to ARDUINO_IO[1]\nset_location_assignment PIN_AB7 -to ARDUINO_IO[2]\nset_location_assignment PIN_AB8 -to ARDUINO_IO[3]\nset_location_assignment PIN_AB9 -to ARDUINO_IO[4]\nset_location_assignment PIN_Y10 -to ARDUINO_IO[5]\nset_location_assignment PIN_AA11 -to ARDUINO_IO[6]\nset_location_assignment PIN_AA12 -to ARDUINO_IO[7]\nset_location_assignment PIN_AB17 -to ARDUINO_IO[8]\nset_location_assignment PIN_AA17 -to ARDUINO_IO[9]\nset_location_assignment PIN_AB19 -to ARDUINO_IO[10]\nset_location_assignment PIN_AA19 -to ARDUINO_IO[11]\nset_location_assignment PIN_Y19 -to ARDUINO_IO[12]\nset_location_assignment PIN_AB20 -to ARDUINO_IO[13]\nset_location_assignment PIN_AB21 -to ARDUINO_IO[14]\nset_location_assignment PIN_AA20 -to ARDUINO_IO[15]\nset_location_assignment PIN_F16 -to ARDUINO_RESET_N\n\nset_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top\nset_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top\nset_global_assignment -name PARTITION_COLOR 16764057 -section_id Top\nset_global_assignment -name VERILOG_FILE DE10_LITE_Golden_Top.v\nset_global_assignment -name MIN_CORE_JUNCTION_TEMP 0\nset_global_assignment -name MAX_CORE_JUNCTION_TEMP 85\nset_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"\nset_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"\nset_global_assignment -name BOARD "MAX 10 DE10 - Lite"\nset_global_assignment -name EDA_SIMULATION_TOOL "Questa Intel FPGA (SystemVerilog)"\nset_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation\nset_global_assignment -name EDA_OUTPUT_DATA_FORMAT "SYSTEMVERILOG HDL" -section_id eda_simulation\nset_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing\nset_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol\nset_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity\nset_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan\nset_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to ARDUINO_IO[0]\nset_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to ARDUINO_IO[1]\nset_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to ARDUINO_IO[2]\nset_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to ARDUINO_IO[3]\nset_global_assignment -name SYSTEMVERILOG_FILE Keypad.sv\nset_global_assignment -name SYSTEMVERILOG_FILE Combo.sv\n\nset_instance_assignment -name RESERVE_PIN AS_INPUT_TRI_STATED -to ARDUINO_IO[3]\nset_instance_assignment -name RESERVE_PIN AS_INPUT_TRI_STATED -to ARDUINO_IO[2]\nset_instance_assignment -name RESERVE_PIN AS_INPUT_TRI_STATED -to ARDUINO_IO[1]\nset_instance_assignment -name RESERVE_PIN AS_INPUT_TRI_STATED -to ARDUINO_IO[0]\n\nset_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top<\/code><\/pre>\n
                                                      QPF: KeyLocker.qpf<\/h3>\n
                                                      QUARTUS_VERSION = "24.1"\nDATE = "09:28:28  \u5341\u6708 12, 2025"\n\n# Revisions\n\nPROJECT_REVISION = "KeyLocker"<\/code><\/pre>\n","protected":false},"excerpt":{"rendered":"
                                                      \u4eca\u5929 \u60a8\u8aaa Keypad SafeLocker Keypad SafeLocker has 2 main mo… » \u95b1\u8b80\u5168\u6587<\/a><\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[21,22],"tags":[],"class_list":["post-1098","post","type-post","status-publish","format-standard","hentry","category-21","category-22"],"_links":{"self":[{"href":"https:\/\/vm1.go2see.me\/index.php?rest_route=\/wp\/v2\/posts\/1098","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/vm1.go2see.me\/index.php?rest_route=\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/vm1.go2see.me\/index.php?rest_route=\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/vm1.go2see.me\/index.php?rest_route=\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/vm1.go2see.me\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=1098"}],"version-history":[{"count":8,"href":"https:\/\/vm1.go2see.me\/index.php?rest_route=\/wp\/v2\/posts\/1098\/revisions"}],"predecessor-version":[{"id":1100,"href":"https:\/\/vm1.go2see.me\/index.php?rest_route=\/wp\/v2\/posts\/1098\/revisions\/1100"}],"wp:attachment":[{"href":"https:\/\/vm1.go2see.me\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=1098"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/vm1.go2see.me\/index.php?rest_route=%2Fwp%2Fv2%2Fcategories&post=1098"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/vm1.go2see.me\/index.php?rest_route=%2Fwp%2Fv2%2Ftags&post=1098"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}