{"id":1055,"date":"2025-10-08T21:35:57","date_gmt":"2025-10-08T13:35:57","guid":{"rendered":"https:\/\/vm1.go2see.me\/?p=1055"},"modified":"2025-10-09T09:05:34","modified_gmt":"2025-10-09T01:05:34","slug":"fsm-%e4%bd%9c%e6%a5%ad","status":"publish","type":"post","link":"https:\/\/vm1.go2see.me\/?p=1055","title":{"rendered":"FSM \u4f5c\u696d"},"content":{"rendered":"

FSM<\/h1>\n
flowchart TD\nOPEN(OPEN <br> savePW=1 <br> display_sel = 0)\nLOCKING(LOCKING <br> savePW=1 <br> display_sel = 0<br> load PSW)\nLOCKED(LOCKED<br>saveAT=1<br>display_sel = 1)\nUNLOCKING(UNLOCKING<br>saveAT=1<br>display_sel = 1<br> load ATT & test)\n\nS(.) -->|RESET| OPEN --> | ENTER | LOCKING -->| !ENTER | LOCKED\nLOCKED -->| ENTER | UNLOCKING -->| !ENTER & MATCH |OPEN\nUNLOCKING -->| !ENTER & !MATCH | LOCKED\n<\/code><\/pre>\n
save.sv<\/h2>\n
module safe (\n    input  logic       CLK50,\n    input  logic [1:0] KEY,       \/\/ KEY[0]=N_RESET, KEY[1]=N_ENTER (active low)\n    input  logic [9:0] SW,\n    output logic [9:0] LEDR,\n    output logic [7:0] HEX5, HEX4, HEX3, HEX2, HEX1, HEX0\n);\n\n    \/\/ 1. DE10-lite key signal Invertion\n    assign RESET   = ~KEY[0];      \/\/ active-high reset\n    assign ENTER   = ~KEY[1];      \/\/ active-high enter\n\n    \/\/ 2. Match Logic & LED Hint Info\n    logic MATCH, PREMATCH;\n    logic [3:0] HINT;\n\n    always_comb begin\n        MATCH     = (ATTEMPT == PASSWORD);\n        PREMATCH  = (SW == PASSWORD);\n        HINT[3:0] = 0;\n        for (int i = 0; i < 10; i++)\n            HINT += (SW[i] ^ PASSWORD[i]);\n    end\n\n    \/\/ 3. FSM Integration\n    logic savePW, saveAT, display_sel;\n\n\/\/***** Choose FSM by remark the other(s)\n\/\/    fsm_verilog fsm_1 (\n    fsm_gate fsm_2(\n        .CLK50       (CLK50),\n        .RESET       (RESET),\n        .ENTER       (ENTER),\n        .MATCH       (MATCH),\n        .savePW      (savePW),\n        .saveAT      (saveAT),\n        .display_sel (display_sel)\n    );\n\n    \/\/ 4. Password \/ Attempt Registers\n    logic [9:0] PASSWORD, ATTEMPT;\n    always_ff @(posedge CLK50) begin\n        if (RESET) begin\n            PASSWORD <= 10'b0000000000;\n            ATTEMPT  <= 10'b1111111111;\n        end else begin\n            if (savePW) PASSWORD <= SW;\n            if (saveAT) ATTEMPT  <= SW;\n        end\n    end\n\n    \/\/ 5. assign LED for Debug Output\n    assign LEDR[9]   = MATCH;\n    assign LEDR[8]   = PREMATCH;\n    assign LEDR[7:4] = 4'b00; \/\/unused LEDs, set to 0 or assign anyother debug signals\n    assign LEDR[3:0] = HINT;  \/\/ count error bits of ATTEMPT\n\n    \/\/ 6. HEX Infomation Display\n    localparam logic [47:0] INFO_OPEN   = 48'hF7_C0_8C_86_AB_F7; \/\/ "_OPEn_"\n    localparam logic [47:0] INFO_LOCKED = 48'hC7_C0_C6_89_86_C0; \/\/ "LOCHED"\n    assign {HEX5, HEX4, HEX3, HEX2, HEX1, HEX0} = display_sel ? INFO_LOCKED : INFO_OPEN;\n\nendmodule\n<\/code><\/pre>\n
fsm_gate.sv<\/h2>\n
module fsm_gate (\n    input  logic CLK50,     \/\/ Clock for FF & Sync Reset\n    input  logic RESET,     \/\/ active-high reset signal\n    input  logic ENTER,     \/\/ active-high enter signal\n    input  logic MATCH,     \/\/ attempt == password\n    output logic savePW,    \/\/ Moore output: save password\n    output logic saveAT,    \/\/ Moore output: save attempt\n    output logic display_sel \/\/ Moore output: display selector\n);\n\n    \/\/ 2-bit state encoding, present state & next state\n     logic S1, S0, N1, N0;\n     assign M=MATCH;\n    assign E=ENTER;\n    \/\/ Sequential logic: state register\n    always_ff @(posedge CLK50) begin\n        if (RESET) begin\n                S1 <= 0; S0 <= 0;     \/\/present=0\n        end else begin\n                S1 <= N1; S0 <= N0;   \/\/ present = next\n        end\n    end\n\n    \/\/ Combinational next-state logic\n     \/*\n     N1N0 |S1S0 E M\n     -----------------\n      0 0 | 0 0 0 x\n      0 0 | 1 1 0 1 \n      0 1 | 0 0 1 x      \n      0 1 | 0 1 1 x\n      1 0 | 0 1 0 x\n      1 0 | 1 0 0 x\n      1 0 | 1 1 0 0\n      1 1 | 1 1 1 x\n      1 1 | 1 0 1 x \n      N1 = (~S1&~S0&E)|(S1&~S0&~E)|(S1&S0&~E&~M)|(S1&S0&E)|(S1&~S0&E);\n      N0 = (~S1&~S0&E)|(~S1&S1&E)|(S1&S0&E)|(S1&~S0&E);\n     *\/\n    always_comb begin\n        N1 = (~S1 & S0 & ~E)|(S1 & ~S0 & ~E)|(S1 & S0 & ~E & ~M)|(S1 & S0 & E)|(S1 & ~S0 & E);\n          N0 = (~S1 & ~S0 & E)|(~S1 & S1 & E)|(S1 & S0 & E)|(S1 & ~S0 & E);\n    end\n\n    \/\/ Moore output logic\n    always_comb begin\n        savePW      = ~S1;  \/\/ OPEN or LOCKING\n        saveAT      = S1;   \/\/ LOCKED or UNLOCKING\n        display_sel = S1;  \/\/ 0 for OPEN, 1 otherwise\n    end\n\nendmodule\n<\/code><\/pre>\n
fsm_verilog.sv<\/h2>\n
module fsm_verilog (\n    input  logic CLK50,     \/\/ Clock for FF & Sync Reset\n    input  logic RESET,     \/\/ active-high reset signal\n    input  logic ENTER,     \/\/ active-high enter signal\n    input  logic MATCH,     \/\/ attempt == password\n    output logic savePW,    \/\/ Moore output: save password\n    output logic saveAT,    \/\/ Moore output: save attempt\n    output logic display_sel \/\/ Moore output: display selector\n);\n\n    \/\/ 1. State Enumerating\n    enum int unsigned {\n        OPEN=0, LOCKING=1, LOCKED=2, UNLOCKING = 3\n    } present_state, next_state;\n\n    \/\/ 2. Sequential State Update\n    always_ff @(posedge CLK50) begin\n        if (RESET)\n            present_state <= OPEN;\n        else\n            present_state <= next_state;\n    end\n\n    \/\/ 3. Combinational Next-State Logic\n    always_comb begin\n        \/\/ Default outputs\n        savePW      = 0;\n        saveAT      = 0;\n        display_sel = 0;\n\n        case (present_state)\n            OPEN: begin\n                next_state   = ENTER ? LOCKING : OPEN;\n                savePW      = 1;\n                display_sel = 0;\n            end\n\n            LOCKING: begin\n                next_state   = ENTER ? LOCKING : LOCKED;\n                savePW      = 1;\n                display_sel = 0;\n            end\n\n            LOCKED: begin\n                next_state   = ENTER ? UNLOCKING : LOCKED;\n                saveAT      = 1;\n                display_sel = 1;\n            end\n\n            UNLOCKING: begin\n                next_state   = ENTER ? UNLOCKING :\n                              MATCH ? OPEN : LOCKED;\n                saveAT      = 1;\n                display_sel = 1;\n            end\n\n            default: begin \/\/ prevent failuare if has undefined state\n                next_state   = OPEN;\n                display_sel = 0;\n            end\n        endcase\n    end\n\nendmodule\n<\/code><\/pre>\n
save.qsf<\/h2>\n
# -------------------------------------------------------------------------- #\n#\n# Copyright (C) 2025  Altera Corporation. All rights reserved.\n# Your use of Altera Corporation's design tools, logic functions \n# and other software and tools, and any partner logic \n# functions, and any output files from any of the foregoing \n# (including device programming or simulation files), and any \n# associated documentation or information are expressly subject \n# to the terms and conditions of the Altera Program License \n# Subscription Agreement, the Altera Quartus Prime License Agreement,\n# the Altera IP License Agreement, or other applicable license\n# agreement, including, without limitation, that your use is for\n# the sole purpose of programming logic devices manufactured by\n# Altera and sold by Altera or its authorized distributors.  Please\n# refer to the Altera Software License Subscription Agreements \n# on the Quartus Prime software download page.\n#\n# -------------------------------------------------------------------------- #\n#\n# Quartus Prime\n# Version 24.1std.0 Build 1077 03\/04\/2025 SC Lite Edition\n# Date created = 21:08:46  September 28, 2025\n#\n# -------------------------------------------------------------------------- #\n#\n# Notes:\n#\n# 1) The default values for assignments are stored in the file:\n#       calc_top_assignment_defaults.qdf\n#    If this file doesn't exist, see file:\n#       assignment_defaults.qdf\n#\n# 2) Intel recommends that you do not modify this file. This\n#    file is updated automatically by the Quartus Prime software\n#    and any changes you make may be lost or overwritten.\n#\n# -------------------------------------------------------------------------- #\n\nset_global_assignment -name FAMILY "MAX 10"\nset_global_assignment -name DEVICE 10M50DAF484C7G\nset_global_assignment -name TOP_LEVEL_ENTITY safe\nset_global_assignment -name ORIGINAL_QUARTUS_VERSION 24.1STD.0\nset_global_assignment -name PROJECT_CREATION_TIME_DATE "21:08:46  OCTOBER 6, 2025"\nset_global_assignment -name LAST_QUARTUS_VERSION "24.1std.0 Lite Edition"\nset_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files\nset_global_assignment -name MIN_CORE_JUNCTION_TEMP 0\nset_global_assignment -name MAX_CORE_JUNCTION_TEMP 85\nset_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256\nset_global_assignment -name EDA_SIMULATION_TOOL "Questa Intel FPGA (SystemVerilog)"\nset_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation\nset_global_assignment -name EDA_OUTPUT_DATA_FORMAT "SYSTEMVERILOG HDL" -section_id eda_simulation\nset_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing\nset_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol\nset_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity\nset_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan\n\n#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLK10_ADC\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLK50\n#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLK50_2\n#set_location_assignment PIN_N5 -to CLK10_ADC\nset_location_assignment PIN_P11 -to CLK50\nset_location_assignment PIN_N14 -to CLK50_2\n\n# used IO pin assignment (SW\u3001KEY\u3001LEDR\u3001HEX)\n\n# SW[0]\u2013SW[9] IO_STANDARD & PIN assignment\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[4]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[5]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[6]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[7]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[8]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[9]\nset_location_assignment PIN_C10 -to SW[0]\nset_location_assignment PIN_C11 -to SW[1]\nset_location_assignment PIN_D12 -to SW[2]\nset_location_assignment PIN_C12 -to SW[3]\nset_location_assignment PIN_A12 -to SW[4]\nset_location_assignment PIN_B12 -to SW[5]\nset_location_assignment PIN_A13 -to SW[6]\nset_location_assignment PIN_A14 -to SW[7]\nset_location_assignment PIN_B14 -to SW[8]\nset_location_assignment PIN_F15 -to SW[9]\n\n# KEY[0]\u2013KEY[1] IO_STANDARD & PIN assignment\nset_instance_assignment -name IO_STANDARD "3.3 V SCHMITT TRIGGER" -to KEY[0]\nset_instance_assignment -name IO_STANDARD "3.3 V SCHMITT TRIGGER" -to KEY[1]\nset_location_assignment PIN_B8 -to KEY[0]\nset_location_assignment PIN_A7 -to KEY[1]\n\n# LEDR[0]\u2013LEDR[9] IO_STANDARD & PIN assignment\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[0]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[1]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[2]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[3]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[4]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[5]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[6]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[7]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[8]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[9]\nset_location_assignment PIN_A8 -to LEDR[0]\nset_location_assignment PIN_A9 -to LEDR[1]\nset_location_assignment PIN_A10 -to LEDR[2]\nset_location_assignment PIN_B10 -to LEDR[3]\nset_location_assignment PIN_D13 -to LEDR[4]\nset_location_assignment PIN_C13 -to LEDR[5]\nset_location_assignment PIN_E14 -to LEDR[6]\nset_location_assignment PIN_D14 -to LEDR[7]\nset_location_assignment PIN_A11 -to LEDR[8]\nset_location_assignment PIN_B11 -to LEDR[9]\n\n# HEX0\u2013HEX5 IO_STANDARD & PIN assignment\n# IO_STANDARD\n# HEX0\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[0]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[1]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[2]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[3]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[4]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[5]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[6]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[7]\n# HEX1\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[0]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[1]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[2]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[3]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[4]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[5]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[6]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[7]\n# HEX2\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[0]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[1]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[2]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[3]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[4]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[5]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[6]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[7]\n# HEX3\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[0]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[1]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[2]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[3]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[4]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[5]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[6]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[7]\n# HEX4\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[0]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[1]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[2]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[3]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[4]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[5]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[6]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[7]\n# HEX5\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[0]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[1]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[2]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[3]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[4]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[5]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[6]\nset_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[7]\n# PIN assignment\n# HEX0\nset_location_assignment PIN_C14 -to HEX0[0]\nset_location_assignment PIN_E15 -to HEX0[1]\nset_location_assignment PIN_C15 -to HEX0[2]\nset_location_assignment PIN_C16 -to HEX0[3]\nset_location_assignment PIN_E16 -to HEX0[4]\nset_location_assignment PIN_D17 -to HEX0[5]\nset_location_assignment PIN_C17 -to HEX0[6]\nset_location_assignment PIN_D15 -to HEX0[7]\n# HEX1\nset_location_assignment PIN_C18 -to HEX1[0]\nset_location_assignment PIN_D18 -to HEX1[1]\nset_location_assignment PIN_E18 -to HEX1[2]\nset_location_assignment PIN_B16 -to HEX1[3]\nset_location_assignment PIN_A17 -to HEX1[4]\nset_location_assignment PIN_A18 -to HEX1[5]\nset_location_assignment PIN_B17 -to HEX1[6]\nset_location_assignment PIN_A16 -to HEX1[7]\n# HEX2\nset_location_assignment PIN_B20 -to HEX2[0]\nset_location_assignment PIN_A20 -to HEX2[1]\nset_location_assignment PIN_B19 -to HEX2[2]\nset_location_assignment PIN_A21 -to HEX2[3]\nset_location_assignment PIN_B21 -to HEX2[4]\nset_location_assignment PIN_C22 -to HEX2[5]\nset_location_assignment PIN_B22 -to HEX2[6]\nset_location_assignment PIN_A19 -to HEX2[7]\n# HEX3\nset_location_assignment PIN_F21 -to HEX3[0]\nset_location_assignment PIN_E22 -to HEX3[1]\nset_location_assignment PIN_E21 -to HEX3[2]\nset_location_assignment PIN_C19 -to HEX3[3]\nset_location_assignment PIN_C20 -to HEX3[4]\nset_location_assignment PIN_D19 -to HEX3[5]\nset_location_assignment PIN_E17 -to HEX3[6]\nset_location_assignment PIN_D22 -to HEX3[7]\n# HEX4\nset_location_assignment PIN_F18 -to HEX4[0]\nset_location_assignment PIN_E20 -to HEX4[1]\nset_location_assignment PIN_E19 -to HEX4[2]\nset_location_assignment PIN_J18 -to HEX4[3]\nset_location_assignment PIN_H19 -to HEX4[4]\nset_location_assignment PIN_F19 -to HEX4[5]\nset_location_assignment PIN_F20 -to HEX4[6]\nset_location_assignment PIN_F17 -to HEX4[7]\n# HEX5\nset_location_assignment PIN_J20 -to HEX5[0]\nset_location_assignment PIN_K20 -to HEX5[1]\nset_location_assignment PIN_L18 -to HEX5[2]\nset_location_assignment PIN_N18 -to HEX5[3]\nset_location_assignment PIN_M20 -to HEX5[4]\nset_location_assignment PIN_N19 -to HEX5[5]\nset_location_assignment PIN_N20 -to HEX5[6]\nset_location_assignment PIN_L19 -to HEX5[7]\n\nset_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top\nset_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top\nset_global_assignment -name PARTITION_COLOR 16764057 -section_id Top\n\nset_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top<\/code><\/pre>\n
Add debouncing circuit on key0\/key1<\/h2>\n
module debounce (\n    input  logic clk,\n    input  logic noisy_in,\n    output logic clean_out\n);\n\n    parameter integer COUNT_MAX = 250000; \/\/ Adjust for ~5ms at 50MHz\n\n    logic [$clog2(COUNT_MAX)-1:0] count;\n    logic stable_state;\n\n    always_ff @(posedge clk) begin\n        if (noisy_in != stable_state) begin\n            count <= count + 1;\n            if (count == COUNT_MAX - 1) begin\n                stable_state <= noisy_in;\n                count <= 0;\n            end\n        end else begin\n            count <= 0;\n        end\n    end\n\n    assign clean_out = stable_state;\n\nendmodule\n<\/code><\/pre>\n
then rewrite 1st step of save.sv<\/h3>\n
module safe (\n    input  logic       CLK50,\n    input  logic [1:0] KEY,       \/\/ KEY[0]=N_RESET, KEY[1]=N_ENTER (active low)\n    input  logic [9:0] SW,\n    output logic [9:0] LEDR,\n    output logic [7:0] HEX5, HEX4, HEX3, HEX2, HEX1, HEX0\n);\n\n    \/\/ 1. DE10-lite key signal Invertion\n    logic key0_db, key1_db;\n\n    debounce db0 (\n         .clk       (CLK50),\n         .noisy_in  (KEY[0]),\n         .clean_out (key0_db)\n    );\n\n    debounce db1 (\n         .clk       (CLK50),\n         .noisy_in  (KEY[1]),\n         .clean_out (key1_db)\n    );\n\n    assign RESET = ~key0_db; \/\/ active-high reset\n    assign ENTER = ~key1_db; \/\/ active-high enter\n\n    \/\/ 2. Match Logic & LED Hint Info\n    logic MATCH, PREMATCH;\n    logic [3:0] HINT;\n\n    always_comb begin\n        MATCH     = (ATTEMPT == PASSWORD);\n        PREMATCH  = (SW == PASSWORD);\n        HINT[3:0] = 0;\n        for (int i = 0; i < 10; i++)\n            HINT += (SW[i] ^ PASSWORD[i]);\n    end\n\n    \/\/ 2. FSM Integration\n    logic savePW, saveAT, display_sel;\n\n\/\/***** Choose FSM by remark the other(s)\n    fsm_verilog fsm_1 (\n\/\/    fsm_gate fsm_2(\n        .CLK50       (CLK50),\n        .RESET       (RESET),\n        .ENTER       (ENTER),\n        .MATCH       (MATCH),\n        .savePW      (savePW),\n        .saveAT      (saveAT),\n        .display_sel (display_sel)\n    );\n\n    \/\/ 3. Password \/ Attempt Registers\n    logic [9:0] PASSWORD, ATTEMPT;\n    always_ff @(posedge CLK50) begin\n        if (RESET) begin\n            PASSWORD <= 10'b0000000000;\n            ATTEMPT  <= 10'b1111111111;\n        end else begin\n            if (savePW) PASSWORD <= SW;\n            if (saveAT) ATTEMPT  <= SW;\n        end\n    end\n\n    \/\/ 4. assign LED for Debug Output\n    assign LEDR[9]   = MATCH;\n    assign LEDR[8]   = PREMATCH;\n    assign LEDR[7:4] = 4'b00; \/\/unused LEDs, set to 0 or assign anyother debug signals\n    assign LEDR[3:0] = HINT;  \/\/ count error bits of ATTEMPT\n\n    \/\/ 5. HEX Infomation Display\n    localparam logic [47:0] INFO_OPEN   = 48'hF7_C0_8C_86_AB_F7; \/\/ "_OPEn_"\n    localparam logic [47:0] INFO_LOCKED = 48'hC7_C0_C6_89_86_C0; \/\/ "LOCHED"\n    assign {HEX5, HEX4, HEX3, HEX2, HEX1, HEX0} = display_sel ? INFO_LOCKED : INFO_OPEN;\n\nendmodule\n<\/code><\/pre>\n","protected":false},"excerpt":{"rendered":"
FSM flowchart TD OPEN(OPEN <br> savePW=1 <br&g… » \u95b1\u8b80\u5168\u6587<\/a><\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[21],"tags":[],"class_list":["post-1055","post","type-post","status-publish","format-standard","hentry","category-21"],"_links":{"self":[{"href":"https:\/\/vm1.go2see.me\/index.php?rest_route=\/wp\/v2\/posts\/1055","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/vm1.go2see.me\/index.php?rest_route=\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/vm1.go2see.me\/index.php?rest_route=\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/vm1.go2see.me\/index.php?rest_route=\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/vm1.go2see.me\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=1055"}],"version-history":[{"count":13,"href":"https:\/\/vm1.go2see.me\/index.php?rest_route=\/wp\/v2\/posts\/1055\/revisions"}],"predecessor-version":[{"id":1058,"href":"https:\/\/vm1.go2see.me\/index.php?rest_route=\/wp\/v2\/posts\/1055\/revisions\/1058"}],"wp:attachment":[{"href":"https:\/\/vm1.go2see.me\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=1055"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/vm1.go2see.me\/index.php?rest_route=%2Fwp%2Fv2%2Fcategories&post=1055"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/vm1.go2see.me\/index.php?rest_route=%2Fwp%2Fv2%2Ftags&post=1055"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}