{"id":1045,"date":"2025-10-05T20:31:46","date_gmt":"2025-10-05T12:31:46","guid":{"rendered":"https:\/\/vm1.go2see.me\/?p=1045"},"modified":"2025-10-05T22:28:52","modified_gmt":"2025-10-05T14:28:52","slug":"lab-5-combination-lock-part-1","status":"publish","type":"post","link":"https:\/\/vm1.go2see.me\/?p=1045","title":{"rendered":"Lab 5: Combination Lock Part 1"},"content":{"rendered":"

Lab 5: Combination Lock Part 1<\/h1>\n
\n

Modified from Digital Design and Computer Architecture: RISC-V Edition (Harris & Harris, Elsevier \u00a9 2021)<\/p>\n<\/blockquote>\n

Objective<\/h2>\n

The purpose of this lab is learn to design a small Moore FSM and accompanying combinational logic circuit. You will use both manual gate-level design and behavioural SystemVerilog design with Quartus. <\/p>\n

In this lab you will design a circuit that locks and unlocks a safe that you might find in a hotel room. <\/p>\n

To use the safe, you place an item inside, close the door and enter any combination as a 10-bit password to lock the safe. To retrieve your item, you enter the same password again to unlock the safe. The process can be repeated as often as desired, each time using any combination you want. <\/p>\n

1. Overall Operation<\/h3>\n
    \n
  • \n

    Inputs: <\/p>\n

    CLK50: automatically generated 50MHz clock<\/p>\n

    SW[9:0]: 10-bit user-entered numeric value<\/p>\n

    KEY[0]: synchronous RESET<\/p>\n

    KEY[1] : ENTER <\/p>\n<\/li>\n

  • \n

    Outputs: <\/p>\n

    HEX5 to HEX0\uff1a user interface, displays LOCHED<\/code> or _OPEn_<\/code><\/p>\n

    LEDR[9] : MATCH<\/code> displays (ATTEMPT==PASSWORD<\/code>) <\/p>\n

    LEDR[8]: PREMATCH<\/code> displays (SW==PASSWORD<\/code>) <\/p>\n

    LEDR[3:0]: COUNT=count_ones<\/code>(ATTEMPT XOR PASSWORD<\/code>) <\/p>\n<\/li>\n

  • \n

    State Bits: <\/p>\n

    PASSWORD: 10-bit user-entered password to unlock the safe<\/p>\n

    ATTEMPT: 10-bit user-entered attempt to unlock the safe <\/p>\n

    CURRENT_STATE: as many bits as required for FSM<\/p>\n<\/li>\n<\/ul>\n

    Operation: <\/p>\n

      \n
    • 50MHz clock drives all flip-flops in CURRENT_STATE, PASSWORD and ATTEMPT<\/li>\n
    • Synchronous reset occurs when RESET is low:\n
        \n
      • CURRENT_STATE changes to the OPEN state<\/li>\n
      • ATTEMPT is set to all 1s<\/li>\n
      • PASSWORD is cleared to all 0s<\/li>\n<\/ul>\n<\/li>\n
      • The FSM has two primary states<\/code>, LOCKED and OPEN\n
          \n
        • User must press and release ENTER<\/strong> to switch to the other primary state<\/li>\n
        • LOCKED<\/code>: displays LOCHED and stores SW as ATTEMPT when ENTER<\/strong> pressed <\/li>\n
        • OPEN<\/code>: displays _OPEn_ <\/code>and stores SW as PASSWORD when ENTER<\/strong> pressed<\/li>\n
        • OPEN<\/code> –> LOCKED<\/code> transitions when ENTER<\/strong> is pressed<\/li>\n
        • LOCKED<\/code> –> OPEN<\/code> transitions when ENTER<\/strong> is pressed and MATCH<\/code><\/li>\n<\/ul>\n<\/li>\n
        • The FSM has additional states<\/strong> (as many as required)\n
            \n
          • The role of these states is to wait for the user to release ENTER<\/strong><\/li>\n
          • Without these, the FSM races between the two primary states while ENTER<\/strong> is pressed<\/li>\n<\/ul>\n<\/li>\n
          • Diagnostic display (for testing and safe cracking)\n
              \n
            • LEDR[9] displays MATCH to indicate when ATTEMPT == PASSWORD<\/li>\n
            • LEDR[8] displays PREMATCH to indicate when SW == PASSWORD<\/li>\n
            • LEDR[3:0] displays COUNT, the number of incorrect ATTEMPT bits<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n

              2. Combinational Logic<\/h3>\n

              Write one always_comb block to: <\/p>\n

                \n
              • Compute MATCH, PREMATCH, and COUNT\n
                  \n
                • Use inputs SW, ATTEMPT and PASSWORD<\/li>\n<\/ul>\n<\/li>\n
                • Connect these to LEDR<\/li>\n<\/ul>\n

                  3. Registers<\/h3>\n

                  Using the CLK50, RESET and other signals noted below, write one always_ff block to: <\/p>\n

                    \n
                  • Update PASSWORD register\n
                      \n
                    • When logic signal savePW<\/strong> is set, save the value of SW to PASSWORD<\/li>\n<\/ul>\n<\/li>\n
                    • Update ATTEMPT register\n
                        \n
                      • When logic signal saveAT<\/strong> is set, save the value of SW to ATTEMPT<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n

                        4. Manual FSM Design<\/h3>\n

                        On paper, using the Moore Machine FSM model, follow the FSM design process: <\/p>\n

                          \n
                        • Determine what FSM inputs are required <\/li>\n
                        • Determine what FSM outputs are required <\/li>\n
                        • Draw the State Diagram needed to control the safe <\/li>\n
                        • Convert the State Diagram to a State Table that clearly shows the next states and all outputs <\/li>\n
                        • Write down your desired State Encoding <\/li>\n
                        • Convert the State Table to a State Table with State Encodings <\/li>\n
                        • Convert the State Table with State Encodings into Karnaugh maps <\/li>\n
                        • From the Karnaugh Map, determine the sum-of-product logic equations for\n
                            \n
                          • All next-state bits <\/li>\n
                          • All output bits<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n

                            Create a SystemVerilog module for the FSM including all necessary inputs and outputs. Don\u2019t forget the clock and reset signals! <\/p>\n

                            module fsm_gates( \n    input logic xxx,\n    \/\/ etc \n    output logic zzz\uff0c\n    \/\/ etc \n); <\/code><\/pre>\n
                            5. Putting it All Together, Part One<\/h3>\n
                            Create a new Quartus project and top-level module the following declaration:<\/p>\n
                            module safe(\n    input logic. CLK50, \n    input logic  [1:0] KEY, \n    input logic  [9:0] SW, \n    output logic [9:0] LEDR, \n    output logic [7:0] HEX5, \n    output logic [7:0] HEX4, \n    output logic [7:0] HEX3, \n    output logic [7:0] HEX2, \n    output logic [7:0] HEX1, \n    output logic [7:0] HEX0 \n);<\/code><\/pre>\n
                            Inside the safe module, create an instance of your fsm module.
                            \nNormally, you would write a testbench for each module to fully test it out. <\/p>\n
                            However, testing sequential logic can be challenging. However, for expedience, we will forgot writing a testbench for this lab.
                            \nInstead, compile your project in Quartus, program your FPGA board, and test it. <\/p>\n
                            Debugging:<\/h4>\n
                            At this stage, it is extremely unlikely you will get it to work \u2013 don\u2019t let that discourage you.
                            \nCheck over your work, especially the manual design process of the FSM. If you notice any errors, correct your logic equations and update your SystemVerilog code.<\/p>\n
                            6. Putting it All Together, Part Two<\/h3>\n
                            In this section, instead of manually creating the FSM logic, write a SystemVerilog module named fsm_verilog<\/strong> that follows directly from the State Diagram or the State Table. Use as many always_ff and\/or always_comb blocks as you need.
                            \nIn your top-level safe module, replace the fsm_gates module with fsm_verilog. Compile the project, program the board, and test it. <\/p>\n
                            Debugging:<\/h4>\n
                            An FSM written this way is much easier to debug and alter. It is also more descriptive, making it easier to get your FSM to work. Instead of worrying about state assignment and extracting correct logic equations from the Karnaugh maps, you can focus on describing the correct state transitions. <\/p>\n
                            7. What to Turn In and Demonstrate<\/h3>\n
                            TBD.<\/p>\n
                            \n
                            Step-by-Step Strategy<\/h2>\n
                            1. Combinational Logic Block<\/h3>\n
                            Create an always_comb<\/code> block to compute:<\/p>\n
                            verilog<\/p>\n
                            always_comb begin\n    MATCH    = (ATTEMPT == PASSWORD);\n    PREMATCH = (SW == PASSWORD);\n    COUNT    = 0;\n    for (int i = 0; i < 10; i++)\n        COUNT += ATTEMPT[i] ^ PASSWORD[i];\n\n    LEDR[9]   = MATCH;\n    LEDR[8]   = PREMATCH;\n    LEDR[3:0] = COUNT;\nend<\/code><\/pre>\n
                            2. Register Update Block<\/h3>\n
                            Use always_ff<\/code> for synchronous updates:<\/p>\n
                            verilog<\/p>\n
                            always_ff @(posedge CLK50) begin\n    if (!RESET) begin\n        PASSWORD <= 10'b0000000000;\n        ATTEMPT <= 10'b1111111111;\n    end else begin\n        if (savePW)\n            PASSWORD <= SW;\n        if (saveAT)\n            ATTEMPT <= SW;\n    end\nend<\/code><\/pre>\n
                            3. Manual FSM Design<\/h3>\n
                            Inputs:<\/h4>\n
                              \n
                            • ENTER<\/code>, RESET<\/code>, MATCH<\/code><\/li>\n<\/ul>\n
                              Outputs:<\/h4>\n
                                \n
                              • savePW<\/code>, saveAT<\/code>, display_state<\/code><\/li>\n<\/ul>\n
                                States:<\/h4>\n
                                  \n
                                • OPEN<\/code>, WAIT_OPEN_RELEASE<\/code>, LOCKED<\/code>, WAIT_LOCK_RELEASE<\/code>, CHECK_MATCH<\/code><\/li>\n<\/ul>\n
                                  State Diagram:<\/h4>\n
                                    \n
                                  • OPEN<\/code> \u2192 (ENTER) \u2192 WAIT_OPEN_RELEASE<\/code> \u2192 (ENTER released) \u2192 LOCKED<\/code><\/li>\n
                                  • LOCKED<\/code> \u2192 (ENTER) \u2192 CHECK_MATCH<\/code> \u2192 (MATCH) \u2192 WAIT_LOCK_RELEASE<\/code> \u2192 (ENTER released) \u2192 OPEN<\/code><\/li>\n
                                  • If no MATCH, stay in LOCKED<\/code><\/li>\n<\/ul>\n
                                    Encoding Example:<\/h4>\n
                                    verilog<\/p>\n
                                    typedef enum logic [2:0] {\n    OPEN              = 3'b000,\n    WAIT_OPEN_RELEASE = 3'b001,\n    LOCKED            = 3'b010,\n    CHECK_MATCH       = 3'b011,\n    WAIT_LOCK_RELEASE = 3'b100\n} state_t;<\/code><\/pre>\n
                                    FSM Logic (fsm_verilog):<\/h4>\n
                                    verilog<\/p>\n
                                    module fsm_verilog(\n    input  logic CLK50, RESET, ENTER, MATCH,\n    output logic savePW, saveAT,\n    output state_t CURRENT_STATE\n);\n    state_t state, next;\n\n    always_ff @(posedge CLK50 or negedge RESET) begin\n        if (!RESET)\n            state <= OPEN;\n        else\n            state <= next;\n    end\n\n    always_comb begin\n        savePW = 0;\n        saveAT = 0;\n        case (state)\n            OPEN: begin\n                if (ENTER) next = WAIT_OPEN_RELEASE;\n                else       next = OPEN;\n                savePW = ENTER;\n            end\n            WAIT_OPEN_RELEASE: begin\n                if (!ENTER) next = LOCKED;\n                else        next = WAIT_OPEN_RELEASE;\n            end\n            LOCKED: begin\n                if (ENTER) next = CHECK_MATCH;\n                else       next = LOCKED;\n                saveAT = ENTER;\n            end\n            CHECK_MATCH: begin\n                if (MATCH) next = WAIT_LOCK_RELEASE;\n                else       next = LOCKED;\n            end\n            WAIT_LOCK_RELEASE: begin\n                if (!ENTER) next = OPEN;\n                else        next = WAIT_LOCK_RELEASE;\n            end\n            default: next = OPEN;\n        endcase\n    end\nendmodule<\/code><\/pre>\n
                                    4. Top-Level Integration<\/h2>\n
                                    verilog<\/p>\n
                                    module safe(\n    input  logic CLK50,\n    input  logic [1:0] KEY,\n    input  logic [9:0] SW,\n    output logic [9:0] LEDR,\n    output logic [7:0] HEX5, HEX4, HEX3, HEX2, HEX1, HEX0\n);\n    logic [9:0] PASSWORD, ATTEMPT;\n    logic MATCH, PREMATCH;\n    logic [3:0] COUNT;\n    logic savePW, saveAT;\n\n    \/\/ Instantiate FSM\n    fsm_verilog fsm_inst(\n        .CLK50(CLK50),\n        .RESET(KEY[0]),\n        .ENTER(KEY[1]),\n        .MATCH(MATCH),\n        .savePW(savePW),\n        .saveAT(saveAT)\n    );\n\n    \/\/ Combinational logic\n    always_comb begin\n        MATCH    = (ATTEMPT == PASSWORD);\n        PREMATCH = (SW == PASSWORD);\n        COUNT    = 0;\n        for (int i = 0; i < 10; i++)\n            COUNT += ATTEMPT[i] ^ PASSWORD[i];\n\n        LEDR[9]   = MATCH;\n        LEDR[8]   = PREMATCH;\n        LEDR[3:0] = COUNT;\n    end\n\n    \/\/ Register logic\n    always_ff @(posedge CLK50) begin\n        if (!KEY[0]) begin\n            PASSWORD <= 10'b0000000000;\n            ATTEMPT <= 10'b1111111111;\n        end else begin\n            if (savePW) PASSWORD <= SW;\n            if (saveAT) ATTEMPT <= SW;\n        end\n    end\nendmodule<\/code><\/pre>\n
                                    FSM State Diagram<\/h2>\n
                                    Here\u2019s a conceptual sketch of the Moore FSM for your safe:<\/p>\n
                                    \u7a0b\u5f0f\u78bc<\/p>\n
                                                +------------------+\n            |                  |\n            |      OPEN        |\n            |  Display: _OPEn_ |\n            +--------+---------+\n                     |\n                     | ENTER pressed\n                     v\n        +------------+-------------+\n        |                          |\n        |   WAIT_OPEN_RELEASE      |\n        | (wait for ENTER release) |\n        +------------+-------------+\n                     |\n                     v\n            +--------+---------+\n            |                  |\n            |     LOCKED       |\n            |  Display: LOCHED |\n            +--------+---------+\n                     |\n                     | ENTER pressed\n                     v\n            +--------+---------+\n            |                  |\n            |   CHECK_MATCH    |\n            |  (ATTEMPT==PW?)  |\n            +--------+---------+\n                     |\n             +-------+-------+\n             |               |\n         MATCH=1         MATCH=0\n             |               |\n             v               v\n+------------------+     +--------+---------+\n| WAIT_LOCK_RELEASE|     |     LOCKED       |\n| (wait for release)|     |  Display: LOCHED|\n+------------------+     +------------------+\n             |\n             v\n         +---+---+\n         | OPEN  |\n         +-------+<\/code><\/pre>\n
                                    Karnaugh Map Setup<\/h2>\n
                                    Let\u2019s assume you use 3 bits to encode states:<\/p>\n\n\n\n\n\n\n\n\n\n
                                    State<\/th>\nEncoding<\/th>\n<\/tr>\n<\/thead>\n
                                    OPEN<\/td>\n000<\/td>\n<\/tr>\n
                                    WAIT_OPEN_RELEASE<\/td>\n001<\/td>\n<\/tr>\n
                                    LOCKED<\/td>\n010<\/td>\n<\/tr>\n
                                    CHECK_MATCH<\/td>\n011<\/td>\n<\/tr>\n
                                    WAIT_LOCK_RELEASE<\/td>\n100<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n
                                    State Table Example<\/h3>\n\n\n\n\n\n\n\n\n\n\n\n\n
                                    Current State<\/th>\nENTER<\/th>\nMATCH<\/th>\nNext State<\/th>\nsavePW<\/th>\nsaveAT<\/th>\n<\/tr>\n<\/thead>\n
                                    OPEN<\/td>\n0<\/td>\nX<\/td>\nOPEN<\/td>\n0<\/td>\n0<\/td>\n<\/tr>\n
                                    OPEN<\/td>\n1<\/td>\nX<\/td>\nWAIT_OPEN_RELEASE<\/td>\n1<\/td>\n0<\/td>\n<\/tr>\n
                                    WAIT_OPEN_REL<\/td>\n0<\/td>\nX<\/td>\nLOCKED<\/td>\n0<\/td>\n0<\/td>\n<\/tr>\n
                                    LOCKED<\/td>\n0<\/td>\nX<\/td>\nLOCKED<\/td>\n0<\/td>\n0<\/td>\n<\/tr>\n
                                    LOCKED<\/td>\n1<\/td>\nX<\/td>\nCHECK_MATCH<\/td>\n0<\/td>\n1<\/td>\n<\/tr>\n
                                    CHECK_MATCH<\/td>\nX<\/td>\n0<\/td>\nLOCKED<\/td>\n0<\/td>\n0<\/td>\n<\/tr>\n
                                    CHECK_MATCH<\/td>\nX<\/td>\n1<\/td>\nWAIT_LOCK_RELEASE<\/td>\n0<\/td>\n0<\/td>\n<\/tr>\n
                                    WAIT_LOCK_REL<\/td>\n0<\/td>\nX<\/td>\nOPEN<\/td>\n0<\/td>\n0<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n
                                    Karnaugh Map for Next State Bits<\/h3>\n
                                    Let\u2019s say you\u2019re solving for NS[0]<\/code> (next state bit 0). You\u2019d fill in a 4-variable K-map using:<\/p>\n
                                      \n
                                    • Current state bits: S2 S1 S0<\/code><\/li>\n
                                    • Inputs: ENTER<\/code>, MATCH<\/code><\/li>\n<\/ul>\n
                                      Each cell in the K-map represents a combination of these inputs, and you fill in the value of NS[0]<\/code> from the state table.<\/p>\n
                                      Once filled, you simplify using grouping rules to extract the SOP (Sum of Products) expression.<\/p>\n
                                      HEX Display Logic<\/h2>\n
                                      To display "LOCHED"<\/code> and "_OPEn_"<\/code>, you\u2019ll need a segment decoder for each character. For example:<\/p>\n\n\n\n\n\n\n\n\n\n\n\n\n\n
                                      Character<\/th>\nHEX Code<\/th>\n<\/tr>\n<\/thead>\n
                                      L<\/td>\n0b01110011<\/td>\n<\/tr>\n
                                      O<\/td>\n0b00111111<\/td>\n<\/tr>\n
                                      C<\/td>\n0b01001110<\/td>\n<\/tr>\n
                                      H<\/td>\n0b01110110<\/td>\n<\/tr>\n
                                      E<\/td>\n0b01111001<\/td>\n<\/tr>\n
                                      D<\/td>\n0b01011110<\/td>\n<\/tr>\n
                                      _<\/td>\n0b00001000<\/td>\n<\/tr>\n
                                      P<\/td>\n0b01110011<\/td>\n<\/tr>\n
                                      n<\/td>\n0b01010100<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n
                                      You can use a case statement inside an always_comb<\/code> block to map each character to its 7-segment code.<\/p>\n
                                      Would you like help writing that decoder module next? Or want to walk through a Karnaugh map example for one of the next-state bits?<\/p>\n
                                      ok<\/p>\n
                                      Great! Let\u2019s walk through two things: a Karnaugh map example for one next-state bit, and a segment decoder for displaying "LOCHED"<\/code> and "_OPEn_"<\/code> on HEX displays.<\/p>\n
                                      Karnaugh Map Example: Next-State Bit<\/h2>\n
                                      Let\u2019s say we\u2019re solving for NS[0]<\/code>, the least significant bit of the next state. Assume the current state is encoded as S2 S1 S0<\/code>, and inputs are ENTER<\/code> and MATCH<\/code>.<\/p>\n
                                      We\u2019ll build a 4-variable Karnaugh map:<\/p>\n
                                      Variables:<\/h3>\n
                                        \n
                                      • S2 S1 S0<\/code> \u2192 current state<\/li>\n
                                      • ENTER<\/code> \u2192 input<\/li>\n
                                      • MATCH<\/code> \u2192 input<\/li>\n<\/ul>\n
                                        Step 1: Fill the truth table<\/h3>\n
                                        From your FSM state table, extract the value of NS[0]<\/code> for each combination of inputs and current state.<\/p>\n
                                        Example row:<\/p>\n\n\n\n\n\n
                                        S2<\/th>\nS1<\/th>\nS0<\/th>\nENTER<\/th>\nMATCH<\/th>\nNS[0]<\/th>\n<\/th>\n<\/tr>\n<\/thead>\n
                                        0<\/td>\n0<\/td>\n0<\/td>\n1<\/td>\nX<\/td>\n1<\/td>\n\u2190 OPEN \u2192 WAIT_OPEN_RELEASE<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n
                                        Repeat for all transitions.<\/p>\n
                                        Step 2: Fill Karnaugh map<\/h3>\n
                                        Use the truth table to populate the K-map. Group adjacent 1s to simplify.<\/p>\n
                                        Step 3: Extract SOP expression<\/h3>\n
                                        From the groups, derive a simplified Boolean expression for NS[0]<\/code>. For example:<\/p>\n
                                        text<\/p>\n
                                        NS[0] = S2' S1 ENTER + S2 S0' MATCH<\/code><\/pre>\n
                                        Repeat for NS[1]<\/code> and NS[2]<\/code>.<\/p>\n
                                        HEX Display Decoder<\/h2>\n
                                        Let\u2019s create a decoder to display "LOCHED"<\/code> and "_OPEn_"<\/code>. Each HEX digit maps to a 7-segment code.<\/p>\n
                                        Segment Encoding Table<\/h3>\n\n\n\n\n\n\n\n\n\n\n\n\n\n
                                        Char<\/th>\nHEX Code<\/th>\nSegment<\/th>\n<\/tr>\n<\/thead>\n
                                        L<\/td>\n7’h38<\/td>\n0110000<\/td>\n<\/tr>\n
                                        O<\/td>\n7’h3F<\/td>\n1111110<\/td>\n<\/tr>\n
                                        C<\/td>\n7’h39<\/td>\n0111001<\/td>\n<\/tr>\n
                                        H<\/td>\n7’h76<\/td>\n1110110<\/td>\n<\/tr>\n
                                        E<\/td>\n7’h79<\/td>\n1111001<\/td>\n<\/tr>\n
                                        D<\/td>\n7’h5E<\/td>\n1011110<\/td>\n<\/tr>\n
                                        _<\/td>\n7’h08<\/td>\n0001000<\/td>\n<\/tr>\n
                                        P<\/td>\n7’h73<\/td>\n1110011<\/td>\n<\/tr>\n
                                        n<\/td>\n7’h54<\/td>\n1010100<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n
                                        Decoder Module<\/h3>\n
                                        verilog<\/p>\n
                                        function logic [7:0] char_to_hex(input logic [2:0] char_index, input logic locked);\n    case (char_index)\n        3'd0: char_to_hex = locked ? 7'h38 : 7'h08; \/\/ L or _\n        3'd1: char_to_hex = locked ? 7'h3F : 7'h73; \/\/ O or P\n        3'd2: char_to_hex = locked ? 7'h39 : 7'h08; \/\/ C or _\n        3'd3: char_to_hex = locked ? 7'h76 : 7'h79; \/\/ H or E\n        3'd4: char_to_hex = locked ? 7'h79 : 7'h54; \/\/ E or n\n        3'd5: char_to_hex = locked ? 7'h5E : 7'h08; \/\/ D or _\n        default: char_to_hex = 7'h00;\n    endcase\nendfunction<\/code><\/pre>\n
                                        Usage in safe<\/code> module<\/h3>\n
                                        verilog<\/p>\n
                                        assign HEX5 = char_to_hex(3'd0, locked);\nassign HEX4 = char_to_hex(3'd1, locked);\nassign HEX3 = char_to_hex(3'd2, locked);\nassign HEX2 = char_to_hex(3'd3, locked);\nassign HEX1 = char_to_hex(3'd4, locked);\nassign HEX0 = char_to_hex(3'd5, locked);<\/code><\/pre>\n
                                        You\u2019ll need to define locked<\/code> as a signal from your FSM state.<\/p>\n
                                        \n
                                        Step-by-Step Implementation Plan<\/h2>\n
                                        1. FSM Inputs and Outputs<\/h3>\n
                                        Inputs:<\/strong><\/p>\n
                                          \n
                                        • CLK50<\/code>: System clock<\/li>\n
                                        • KEY[0]<\/code>: Active-low reset<\/li>\n
                                        • KEY[1]<\/code>: ENTER button<\/li>\n
                                        • SW[9:0]<\/code>: User input (password or attempt)<\/li>\n<\/ul>\n
                                          Outputs:<\/strong><\/p>\n
                                            \n
                                          • LEDR[9]<\/code>: MATCH = (ATTEMPT == PASSWORD<\/code>)<\/li>\n
                                          • LEDR[8]<\/code>: PREMATCH = (SW == PASSWORD<\/code>)<\/li>\n
                                          • LEDR[3:0]<\/code>: COUNT = count_ones(ATTEMPT ^ PASSWORD)<\/code><\/li>\n
                                          • HEX0<\/code>: Displays "LOCHED"<\/code> or "_OPEn_"<\/code><\/li>\n<\/ul>\n
                                            Character Breakdown<\/h4>\n\n\n\n\n\n\n\n\n\n\n
                                            HEX Display<\/th>\n"LOCHED"<\/code><\/th>\n"_OPEn_"<\/code><\/th>\n<\/tr>\n<\/thead>\n
                                            HEX5<\/td>\n'L'<\/code><\/td>\n'_'<\/code><\/td>\n<\/tr>\n
                                            HEX4<\/td>\n'O'<\/code><\/td>\n'O'<\/code><\/td>\n<\/tr>\n
                                            HEX3<\/td>\n'C'<\/code><\/td>\n'P'<\/code><\/td>\n<\/tr>\n
                                            HEX2<\/td>\n'H'<\/code><\/td>\n'E'<\/code><\/td>\n<\/tr>\n
                                            HEX1<\/td>\n'E'<\/code><\/td>\n'n'<\/code><\/td>\n<\/tr>\n
                                            HEX0<\/td>\n'D'<\/code><\/td>\n'_'<\/code><\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n
                                            7 Seg. value:<\/h4>\n\n\n\n\n\n\n\n\n\n\n\n\n\n
                                            Char<\/th>\nSegments 1 as light\uff0cbit order: (gfedcba)<\/th>\nHex Value, 
                                            invert since0 as light<\/th>\n<\/tr>\n<\/thead>\n
                                            'L'<\/code><\/td>\n0111000<\/code><\/td>\n~7'h38<\/code><\/td>\n<\/tr>\n
                                            'O'<\/code><\/td>\n0011111<\/code><\/td>\n~7'h3F<\/code><\/td>\n<\/tr>\n
                                            'C'<\/code><\/td>\n0110111<\/code><\/td>\n~7'h67<\/code><\/td>\n<\/tr>\n
                                            'H'<\/code><\/td>\n0111100<\/code><\/td>\n~7'h3C<\/code><\/td>\n<\/tr>\n
                                            'E'<\/code><\/td>\n0110110<\/code><\/td>\n~7'h76<\/code><\/td>\n<\/tr>\n
                                            'D'<\/code><\/td>\n0011110<\/code><\/td>\n~7'h3E<\/code><\/td>\n<\/tr>\n
                                            'P'<\/code><\/td>\n0111001<\/code><\/td>\n~7'h79<\/code><\/td>\n<\/tr>\n
                                            'n'<\/code><\/td>\n0101010<\/code><\/td>\n~7'h2A<\/code><\/td>\n<\/tr>\n
                                            '_'<\/code><\/td>\n0001000<\/code><\/td>\n~7'h08<\/code><\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n
                                            HEX5-0 control be:<\/h4>\n
                                            always_comb begin\n    if (CURRENT_STATE == LOCKED) begin\n        HEX5 = ~7'h38; \/\/ L\n        HEX4 = ~7'h3F; \/\/ 0 (0 as O)\n        HEX3 = ~7'h67; \/\/ C\n        HEX2 = ~7'h3C; \/\/ H (H as K)\n        HEX1 = ~7'h76; \/\/ E\n        HEX0 = ~7'h3E; \/\/ d (d as D)\n    end else begin \/\/ OPEN\n        HEX5 = ~7'h08; \/\/ _\n        HEX4 = ~7'h3F; \/\/ O\n        HEX3 = ~7'h79; \/\/ P\n        HEX2 = ~7'h76; \/\/ E\n        HEX1 = ~7'h2A; \/\/ n\n        HEX0 = ~7'h08; \/\/ _\n    end\nend\n<\/code><\/pre>\n
                                            2. Combinational Logic Block<\/h3>\n
                                            always_comb begin\n    MATCH    = (ATTEMPT == PASSWORD);\n    PREMATCH = (SW == PASSWORD);\n    COUNT    = $countones(ATTEMPT ^ PASSWORD); \/\/ or use a loop if $countones unsupported\n\n    LEDR[9]   = MATCH;\n    LEDR[8]   = PREMATCH;\n    LEDR[3:0] = COUNT;\nend<\/code><\/pre>\n
                                            3. Register Update Block<\/h3>\n
                                            always_ff @(posedge CLK50) begin\n    if (!KEY[0]) begin \/\/ synchronous reset\n        PASSWORD      <= 10'b0000000000;\n        ATTEMPT       <= 10'b1111111111;\n        CURRENT_STATE <= OPEN;\n    end else begin\n        if (savePW)\n            PASSWORD <= SW;\n        if (saveAT)\n            ATTEMPT <= SW;\n    end\nend<\/code><\/pre>\n
                                            4. Manual FSM Design (Moore Model)<\/h3>\n
                                            State Definitions<\/h4>\n\n\n\n\n\n\n\n\n
                                            State<\/th>\nDescription<\/th>\n<\/tr>\n<\/thead>\n
                                            OPEN<\/code><\/td>\nSafe is unlocked<\/td>\n<\/tr>\n
                                            WAIT_OPEN<\/code><\/td>\nWait for ENTER release after storing PASSWORD<\/td>\n<\/tr>\n
                                            LOCKED<\/code><\/td>\nSafe is locked<\/td>\n<\/tr>\n
                                            WAIT_LOCKED<\/code><\/td>\nWait for ENTER release after storing ATTEMPT<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n
                                            State Diagram<\/h4>\n
                                            \u7a0b\u5f0f\u78bc<\/p>\n
                                            OPEN --(ENTER)--> WAIT_OPEN --(release)--> LOCKED\nLOCKED --(ENTER & MATCH)--> WAIT_LOCKED --(release)--> OPEN<\/code><\/pre>\n
                                            graph LR\nOPEN -->|ENTER| WAIT_OPEN -->|release| LOCKED\nLOCKED -->|ENTER & MATCH| WAIT_LOCKED -->|release| OPEN\n<\/code><\/pre>\n
                                            State Encoding<\/h4>\n
                                            typedef enum logic [1:0] {\n    OPEN        = 2'b00,\n    WAIT_OPEN   = 2'b01,\n    LOCKED      = 2'b10,\n    WAIT_LOCKED = 2'b11\n} state_t;<\/code><\/pre>\n
                                            5. FSM Logic (Manual Gate-Level)<\/h3>\n
                                            Use Karnaugh maps to derive SOP equations for next-state bits and outputs. Then implement them in fsm_gates<\/code> using basic gates or assign<\/code> statements.<\/p>\n
                                            6. FSM Logic (Behavioral)<\/h3>\n
                                            module fsm_verilog(\n    input logic CLK50, RESET, ENTER,\n    input logic MATCH,\n    output logic savePW, saveAT,\n    output logic [1:0] CURRENT_STATE\n);\n    typedef enum logic [1:0] {OPEN, WAIT_OPEN, LOCKED, WAIT_LOCKED} state_t;\n    state_t state, next_state;\n\n    always_ff @(posedge CLK50) begin\n        if (!RESET)\n            state <= OPEN;\n        else\n            state <= next_state;\n    end\n\n    always_comb begin\n        savePW = 0;\n        saveAT = 0;\n        case (state)\n            OPEN: begin\n                if (ENTER) begin\n                    savePW    = 1;\n                    next_state = WAIT_OPEN;\n                end else\n                    next_state = OPEN;\n            end\n            WAIT_OPEN: next_state = (ENTER) ? WAIT_OPEN : LOCKED;\n\n            LOCKED: begin\n                if (ENTER && MATCH) begin\n                    saveAT    = 1;\n                    next_state = WAIT_LOCKED;\n                end else\n                    next_state = LOCKED;\n            end\n            WAIT_LOCKED: next_state = (ENTER) ? WAIT_LOCKED : OPEN;\n        endcase\n    end\n\n    assign CURRENT_STATE = state;\nendmodule<\/code><\/pre>\n
                                            7. Top-Level Module safe<\/code><\/h3>\n
                                            module safe(\n    input logic CLK50,\n    input logic [1:0] KEY,\n    input logic [9:0] SW,\n    output logic [9:0] LEDR,\n    output logic [7:0] HEX5, HEX4, HEX3, HEX2, HEX1, HEX0\n);\n    logic [9:0] PASSWORD, ATTEMPT;\n    logic MATCH, PREMATCH;\n    logic [3:0] COUNT;\n    logic savePW, saveAT;\n    logic [1:0] CURRENT_STATE;\n\n    \/\/ Instantiate FSM\n    fsm_verilog fsm_inst(\n        .CLK50(CLK50),\n        .RESET(KEY[0]),\n        .ENTER(KEY[1]),\n        .MATCH(MATCH),\n        .savePW(savePW),\n        .saveAT(saveAT),\n        .CURRENT_STATE(CURRENT_STATE)\n    );\n\n    \/\/ Register logic\n    always_ff @(posedge CLK50) begin\n        if (!KEY[0]) begin\n            PASSWORD <= 10'b0000000000;\n            ATTEMPT  <= 10'b1111111111;\n        end else begin\n            if (savePW) PASSWORD <= SW;\n            if (saveAT) ATTEMPT  <= SW;\n        end\n    end\n\n    \/\/ Combinational logic\n    always_comb begin\n        MATCH    = (ATTEMPT == PASSWORD);\n        PREMATCH = (SW == PASSWORD);\n        COUNT    = $countones(ATTEMPT ^ PASSWORD);\n\n        LEDR[9]   = MATCH;\n        LEDR[8]   = PREMATCH;\n        LEDR[3:0] = COUNT;\n    end\n\n    \/\/ HEX0 display logic (simplified)\n    assign HEX0 = (CURRENT_STATE == LOCKED) ? 8'hDE : 8'h0E; \/\/ placeholder for LOCHED\/_OPEn_\nendmodule<\/code><\/pre>\n
                                            Would you like help generating the HEX segment decoder for "LOCHED"<\/code> and "_OPEn_"<\/code> or visualizing the FSM diagram? I can also walk you through Karnaugh map derivation if you’re tackling the manual gate-level version.<\/p>\n
                                            HEX5 to HEX0\uff1a user interface, displays LOCHED<\/code> or _OPEn_<\/code><\/p>\n
                                            To display "LOCHED"<\/code> or "_OPEn_"<\/code> across HEX5 to HEX0, you’ll need to drive each 7-segment display with the correct segment encoding for each character. Here’s how you can implement it in SystemVerilog:<\/p>\n
                                            Segment Mapping for "LOCHED"<\/code> and "_OPEn_"<\/code><\/h2>\n
                                            Each HEX display shows one ASCII-like character using 7 segments. We’ll define segment encodings for each character.<\/p>\n
                                            Character Breakdown<\/h3>\n\n\n\n\n\n\n\n\n\n\n
                                            HEX Display<\/th>\n"LOCHED"<\/code><\/th>\n"_OPEn_"<\/code><\/th>\n<\/tr>\n<\/thead>\n
                                            HEX5<\/td>\n'L'<\/code><\/td>\n'_'<\/code><\/td>\n<\/tr>\n
                                            HEX4<\/td>\n'O'<\/code><\/td>\n'O'<\/code><\/td>\n<\/tr>\n
                                            HEX3<\/td>\n'C'<\/code><\/td>\n'P'<\/code><\/td>\n<\/tr>\n
                                            HEX2<\/td>\n'H'<\/code><\/td>\n'E'<\/code><\/td>\n<\/tr>\n
                                            HEX1<\/td>\n'E'<\/code><\/td>\n'n'<\/code><\/td>\n<\/tr>\n
                                            HEX0<\/td>\n'D'<\/code><\/td>\n'_'<\/code><\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n
                                            Segment Encoding (Common Active-Low)<\/h3>\n
                                            Each character maps to a 7-bit pattern for segments A\u2013G. Here’s a sample encoding table:<\/p>\n\n\n\n\n\n\n\n\n\n\n\n\n\n
                                            Char<\/th>\nSegments (gfedcba)<\/th>\nHex Value<\/th>\n<\/tr>\n<\/thead>\n
                                            'L'<\/code><\/td>\n0111000<\/code><\/td>\n7'h38<\/code><\/td>\n<\/tr>\n
                                            'O'<\/code><\/td>\n0011111<\/code><\/td>\n7'h3F<\/code><\/td>\n<\/tr>\n
                                            'C'<\/code><\/td>\n0110111<\/code><\/td>\n7'h67<\/code><\/td>\n<\/tr>\n
                                            'H'<\/code><\/td>\n0111100<\/code><\/td>\n7'h3C<\/code><\/td>\n<\/tr>\n
                                            'E'<\/code><\/td>\n0110110<\/code><\/td>\n7'h76<\/code><\/td>\n<\/tr>\n
                                            'D'<\/code><\/td>\n0011110<\/code><\/td>\n7'h3E<\/code><\/td>\n<\/tr>\n
                                            'P'<\/code><\/td>\n0111001<\/code><\/td>\n7'h79<\/code><\/td>\n<\/tr>\n
                                            'n'<\/code><\/td>\n0101010<\/code><\/td>\n7'h2A<\/code><\/td>\n<\/tr>\n
                                            '_'<\/code><\/td>\n0001000<\/code><\/td>\n7'h08<\/code><\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n
                                            \n
                                            Note: These encodings assume active-low segments. You may need to invert them (~<\/code>) depending on your board.<\/p>\n<\/blockquote>\n
                                            SystemVerilog Implementation<\/h3>\n
                                            always_comb begin\n    if (CURRENT_STATE == LOCKED) begin\n        HEX5 = ~7'h38; \/\/ L\n        HEX4 = ~7'h3F; \/\/ O\n        HEX3 = ~7'h67; \/\/ C\n        HEX2 = ~7'h3C; \/\/ H\n        HEX1 = ~7'h76; \/\/ E\n        HEX0 = ~7'h3E; \/\/ D\n    end else begin \/\/ OPEN\n        HEX5 = ~7'h08; \/\/ _\n        HEX4 = ~7'h3F; \/\/ O\n        HEX3 = ~7'h79; \/\/ P\n        HEX2 = ~7'h76; \/\/ E\n        HEX1 = ~7'h2A; \/\/ n\n        HEX0 = ~7'h08; \/\/ _\n    end\nend<\/code><\/pre>\n
                                            Would you like a visual layout of the 7-segment characters or help testing this on your FPGA board? I can also help you write a reusable decoder module if you want to support more characters.<\/p>\n","protected":false},"excerpt":{"rendered":"
                                            Lab 5: Combination Lock Part 1 Modified from Digital De… » \u95b1\u8b80\u5168\u6587<\/a><\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[21],"tags":[],"class_list":["post-1045","post","type-post","status-publish","format-standard","hentry","category-21"],"_links":{"self":[{"href":"https:\/\/vm1.go2see.me\/index.php?rest_route=\/wp\/v2\/posts\/1045","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/vm1.go2see.me\/index.php?rest_route=\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/vm1.go2see.me\/index.php?rest_route=\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/vm1.go2see.me\/index.php?rest_route=\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/vm1.go2see.me\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=1045"}],"version-history":[{"count":5,"href":"https:\/\/vm1.go2see.me\/index.php?rest_route=\/wp\/v2\/posts\/1045\/revisions"}],"predecessor-version":[{"id":1047,"href":"https:\/\/vm1.go2see.me\/index.php?rest_route=\/wp\/v2\/posts\/1045\/revisions\/1047"}],"wp:attachment":[{"href":"https:\/\/vm1.go2see.me\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=1045"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/vm1.go2see.me\/index.php?rest_route=%2Fwp%2Fv2%2Fcategories&post=1045"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/vm1.go2see.me\/index.php?rest_route=%2Fwp%2Fv2%2Ftags&post=1045"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}